1bd744d46SAndrew Jones /* SPDX-License-Identifier: GPL-2.0-only */ 2bd744d46SAndrew Jones /* 3bd744d46SAndrew Jones * From Linux arch/riscv/include/asm/mmio.h 4bd744d46SAndrew Jones */ 5bd744d46SAndrew Jones #ifndef _ASMRISCV_IO_H_ 6bd744d46SAndrew Jones #define _ASMRISCV_IO_H_ 7bd744d46SAndrew Jones #include <libcflat.h> 8bd744d46SAndrew Jones 9bd744d46SAndrew Jones #define __iomem 10bd744d46SAndrew Jones 11bd744d46SAndrew Jones /* Generic IO read/write. These perform native-endian accesses. */ 12bd744d46SAndrew Jones #define __raw_writeb __raw_writeb 13bd744d46SAndrew Jones static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 14bd744d46SAndrew Jones { 15bd744d46SAndrew Jones asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); 16bd744d46SAndrew Jones } 17bd744d46SAndrew Jones 18bd744d46SAndrew Jones #define __raw_writew __raw_writew 19bd744d46SAndrew Jones static inline void __raw_writew(u16 val, volatile void __iomem *addr) 20bd744d46SAndrew Jones { 21bd744d46SAndrew Jones asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); 22bd744d46SAndrew Jones } 23bd744d46SAndrew Jones 24bd744d46SAndrew Jones #define __raw_writel __raw_writel 25bd744d46SAndrew Jones static inline void __raw_writel(u32 val, volatile void __iomem *addr) 26bd744d46SAndrew Jones { 27bd744d46SAndrew Jones asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); 28bd744d46SAndrew Jones } 29bd744d46SAndrew Jones 30bd744d46SAndrew Jones #ifdef CONFIG_64BIT 31bd744d46SAndrew Jones #define __raw_writeq __raw_writeq 32bd744d46SAndrew Jones static inline void __raw_writeq(u64 val, volatile void __iomem *addr) 33bd744d46SAndrew Jones { 34bd744d46SAndrew Jones asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); 35bd744d46SAndrew Jones } 36bd744d46SAndrew Jones #endif 37bd744d46SAndrew Jones 38bd744d46SAndrew Jones #define __raw_readb __raw_readb 39bd744d46SAndrew Jones static inline u8 __raw_readb(const volatile void __iomem *addr) 40bd744d46SAndrew Jones { 41bd744d46SAndrew Jones u8 val; 42bd744d46SAndrew Jones 43bd744d46SAndrew Jones asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); 44bd744d46SAndrew Jones return val; 45bd744d46SAndrew Jones } 46bd744d46SAndrew Jones 47bd744d46SAndrew Jones #define __raw_readw __raw_readw 48bd744d46SAndrew Jones static inline u16 __raw_readw(const volatile void __iomem *addr) 49bd744d46SAndrew Jones { 50bd744d46SAndrew Jones u16 val; 51bd744d46SAndrew Jones 52bd744d46SAndrew Jones asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); 53bd744d46SAndrew Jones return val; 54bd744d46SAndrew Jones } 55bd744d46SAndrew Jones 56bd744d46SAndrew Jones #define __raw_readl __raw_readl 57bd744d46SAndrew Jones static inline u32 __raw_readl(const volatile void __iomem *addr) 58bd744d46SAndrew Jones { 59bd744d46SAndrew Jones u32 val; 60bd744d46SAndrew Jones 61bd744d46SAndrew Jones asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); 62bd744d46SAndrew Jones return val; 63bd744d46SAndrew Jones } 64bd744d46SAndrew Jones 65bd744d46SAndrew Jones #ifdef CONFIG_64BIT 66bd744d46SAndrew Jones #define __raw_readq __raw_readq 67bd744d46SAndrew Jones static inline u64 __raw_readq(const volatile void __iomem *addr) 68bd744d46SAndrew Jones { 69bd744d46SAndrew Jones u64 val; 70bd744d46SAndrew Jones 71bd744d46SAndrew Jones asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); 72bd744d46SAndrew Jones return val; 73bd744d46SAndrew Jones } 74bd744d46SAndrew Jones #endif 75bd744d46SAndrew Jones 76*ad435a71SAndrew Jones #define ioremap ioremap 77*ad435a71SAndrew Jones void __iomem *ioremap(phys_addr_t phys_addr, size_t size); 78*ad435a71SAndrew Jones 79bd744d46SAndrew Jones #include <asm-generic/io.h> 80bd744d46SAndrew Jones 81bd744d46SAndrew Jones #endif /* _ASMRISCV_IO_H_ */ 82