1bd744d46SAndrew Jones /* SPDX-License-Identifier: GPL-2.0-only */ 2bd744d46SAndrew Jones #ifndef _ASMRISCV_BARRIER_H_ 3bd744d46SAndrew Jones #define _ASMRISCV_BARRIER_H_ 4bd744d46SAndrew Jones 5bd744d46SAndrew Jones #define RISCV_FENCE(p, s) \ 6bd744d46SAndrew Jones __asm__ __volatile__ ("fence " #p "," #s : : : "memory") 7bd744d46SAndrew Jones 8bd744d46SAndrew Jones /* These barriers need to enforce ordering on both devices or memory. */ 9bd744d46SAndrew Jones #define mb() RISCV_FENCE(iorw,iorw) 10bd744d46SAndrew Jones #define rmb() RISCV_FENCE(ir,ir) 11bd744d46SAndrew Jones #define wmb() RISCV_FENCE(ow,ow) 12bd744d46SAndrew Jones 1322f287f4SAndrew Jones /* These barriers do not need to enforce ordering on devices, just memory. */ 1422f287f4SAndrew Jones #define smp_mb() RISCV_FENCE(rw,rw) 1522f287f4SAndrew Jones #define smp_rmb() RISCV_FENCE(r,r) 1622f287f4SAndrew Jones #define smp_wmb() RISCV_FENCE(w,w) 1722f287f4SAndrew Jones 18*9c92b28eSAndrew Jones #define cpu_relax() __asm__ __volatile__ ("pause") 19*9c92b28eSAndrew Jones 20bd744d46SAndrew Jones #endif /* _ASMRISCV_BARRIER_H_ */ 21