xref: /kvm-unit-tests/lib/riscv/asm/barrier.h (revision 48d5952451de62a4db23cf73024f702cf1a64fc3)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASMRISCV_BARRIER_H_
3 #define _ASMRISCV_BARRIER_H_
4 
5 #define RISCV_FENCE(p, s) \
6 	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
7 
8 /* These barriers need to enforce ordering on both devices or memory. */
9 #define mb()		RISCV_FENCE(iorw,iorw)
10 #define rmb()		RISCV_FENCE(ir,ir)
11 #define wmb()		RISCV_FENCE(ow,ow)
12 
13 /* These barriers do not need to enforce ordering on devices, just memory. */
14 #define smp_mb()	RISCV_FENCE(rw,rw)
15 #define smp_rmb()	RISCV_FENCE(r,r)
16 #define smp_wmb()	RISCV_FENCE(w,w)
17 
18 #define cpu_relax()	__asm__ __volatile__ ("pause")
19 
20 #endif /* _ASMRISCV_BARRIER_H_ */
21