1 /* 2 * Copyright (C) 2013, Red Hat Inc, Michael S. Tsirkin <mst@redhat.com> 3 * 4 * This work is licensed under the terms of the GNU LGPL, version 2. 5 */ 6 #include <linux/pci_regs.h> 7 #include "pci.h" 8 #include "asm/pci.h" 9 10 void pci_cap_walk(struct pci_dev *dev, pci_cap_handler_t handler) 11 { 12 uint8_t cap_offset; 13 uint8_t cap_id; 14 int count = 0; 15 16 cap_offset = pci_config_readb(dev->bdf, PCI_CAPABILITY_LIST); 17 while (cap_offset) { 18 cap_id = pci_config_readb(dev->bdf, cap_offset); 19 assert(cap_id < PCI_CAP_ID_MAX + 1); 20 handler(dev, cap_offset, cap_id); 21 cap_offset = pci_config_readb(dev->bdf, cap_offset + 1); 22 /* Avoid dead loop during cap walk */ 23 assert(++count <= 255); 24 } 25 } 26 27 void pci_msi_set_enable(struct pci_dev *dev, bool enabled) 28 { 29 uint16_t msi_control; 30 uint16_t offset; 31 32 offset = dev->msi_offset; 33 msi_control = pci_config_readw(dev->bdf, offset + PCI_MSI_FLAGS); 34 35 if (enabled) 36 msi_control |= PCI_MSI_FLAGS_ENABLE; 37 else 38 msi_control &= ~PCI_MSI_FLAGS_ENABLE; 39 40 pci_config_writew(dev->bdf, offset + PCI_MSI_FLAGS, msi_control); 41 } 42 43 bool pci_setup_msi(struct pci_dev *dev, uint64_t msi_addr, uint32_t msi_data) 44 { 45 uint16_t msi_control; 46 uint16_t offset; 47 pcidevaddr_t addr; 48 49 assert(dev); 50 51 if (!dev->msi_offset) { 52 printf("MSI: dev 0x%x does not support MSI.\n", dev->bdf); 53 return false; 54 } 55 56 addr = dev->bdf; 57 offset = dev->msi_offset; 58 msi_control = pci_config_readw(addr, offset + PCI_MSI_FLAGS); 59 pci_config_writel(addr, offset + PCI_MSI_ADDRESS_LO, 60 msi_addr & 0xffffffff); 61 62 if (msi_control & PCI_MSI_FLAGS_64BIT) { 63 pci_config_writel(addr, offset + PCI_MSI_ADDRESS_HI, 64 (uint32_t)(msi_addr >> 32)); 65 pci_config_writel(addr, offset + PCI_MSI_DATA_64, msi_data); 66 } else { 67 pci_config_writel(addr, offset + PCI_MSI_DATA_32, msi_data); 68 } 69 70 pci_msi_set_enable(dev, true); 71 72 return true; 73 } 74 75 void pci_cmd_set_clr(struct pci_dev *dev, uint16_t set, uint16_t clr) 76 { 77 uint16_t val = pci_config_readw(dev->bdf, PCI_COMMAND); 78 79 /* No overlap is allowed */ 80 assert((set & clr) == 0); 81 val |= set; 82 val &= ~clr; 83 84 pci_config_writew(dev->bdf, PCI_COMMAND, val); 85 } 86 87 bool pci_dev_exists(pcidevaddr_t dev) 88 { 89 return (pci_config_readw(dev, PCI_VENDOR_ID) != 0xffff && 90 pci_config_readw(dev, PCI_DEVICE_ID) != 0xffff); 91 } 92 93 /* Scan bus look for a specific device. Only bus 0 scanned for now. */ 94 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id) 95 { 96 pcidevaddr_t dev; 97 98 for (dev = 0; dev < PCI_DEVFN_MAX; ++dev) { 99 if (pci_config_readw(dev, PCI_VENDOR_ID) == vendor_id && 100 pci_config_readw(dev, PCI_DEVICE_ID) == device_id) 101 return dev; 102 } 103 104 return PCIDEVADDR_INVALID; 105 } 106 107 uint32_t pci_bar_mask(uint32_t bar) 108 { 109 return (bar & PCI_BASE_ADDRESS_SPACE_IO) ? 110 PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK; 111 } 112 113 uint32_t pci_bar_get(struct pci_dev *dev, int bar_num) 114 { 115 return pci_config_readl(dev->bdf, PCI_BASE_ADDRESS_0 + 116 bar_num * 4); 117 } 118 119 static phys_addr_t __pci_bar_get_addr(struct pci_dev *dev, int bar_num) 120 { 121 uint32_t bar = pci_bar_get(dev, bar_num); 122 uint32_t mask = pci_bar_mask(bar); 123 uint64_t addr = bar & mask; 124 phys_addr_t phys_addr; 125 126 if (pci_bar_is64(dev, bar_num)) 127 addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32; 128 129 phys_addr = pci_translate_addr(dev->bdf, addr); 130 assert(phys_addr != INVALID_PHYS_ADDR); 131 132 return phys_addr; 133 } 134 135 phys_addr_t pci_bar_get_addr(struct pci_dev *dev, int bar_num) 136 { 137 return dev->resource[bar_num]; 138 } 139 140 void pci_bar_set_addr(struct pci_dev *dev, int bar_num, phys_addr_t addr) 141 { 142 int off = PCI_BASE_ADDRESS_0 + bar_num * 4; 143 144 pci_config_writel(dev->bdf, off, (uint32_t)addr); 145 dev->resource[bar_num] = addr; 146 147 if (pci_bar_is64(dev, bar_num)) { 148 assert(bar_num + 1 < PCI_BAR_NUM); 149 pci_config_writel(dev->bdf, off + 4, (uint32_t)(addr >> 32)); 150 dev->resource[bar_num + 1] = dev->resource[bar_num]; 151 } 152 } 153 154 /* 155 * To determine the amount of address space needed by a PCI device, 156 * one must save the original value of the BAR, write a value of 157 * all 1's to the register, and then read it back. The amount of 158 * memory can be then determined by masking the information bits, 159 * performing a bitwise NOT, and incrementing the value by 1. 160 * 161 * The following pci_bar_size_helper() and pci_bar_size() functions 162 * implement the algorithm. 163 */ 164 static uint32_t pci_bar_size_helper(struct pci_dev *dev, int bar_num) 165 { 166 int off = PCI_BASE_ADDRESS_0 + bar_num * 4; 167 uint16_t bdf = dev->bdf; 168 uint32_t bar, val; 169 170 bar = pci_config_readl(bdf, off); 171 pci_config_writel(bdf, off, ~0u); 172 val = pci_config_readl(bdf, off); 173 pci_config_writel(bdf, off, bar); 174 175 return val; 176 } 177 178 phys_addr_t pci_bar_size(struct pci_dev *dev, int bar_num) 179 { 180 uint32_t bar, size; 181 182 size = pci_bar_size_helper(dev, bar_num); 183 if (!size) 184 return 0; 185 186 bar = pci_bar_get(dev, bar_num); 187 size &= pci_bar_mask(bar); 188 189 if (pci_bar_is64(dev, bar_num)) { 190 phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1); 191 size64 = (size64 << 32) | size; 192 193 return ~size64 + 1; 194 } else { 195 return ~size + 1; 196 } 197 } 198 199 bool pci_bar_is_memory(struct pci_dev *dev, int bar_num) 200 { 201 uint32_t bar = pci_bar_get(dev, bar_num); 202 203 return !(bar & PCI_BASE_ADDRESS_SPACE_IO); 204 } 205 206 bool pci_bar_is_valid(struct pci_dev *dev, int bar_num) 207 { 208 return dev->resource[bar_num] != INVALID_PHYS_ADDR; 209 } 210 211 bool pci_bar_is64(struct pci_dev *dev, int bar_num) 212 { 213 uint32_t bar = pci_bar_get(dev, bar_num); 214 215 if (bar & PCI_BASE_ADDRESS_SPACE_IO) 216 return false; 217 218 return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 219 PCI_BASE_ADDRESS_MEM_TYPE_64; 220 } 221 222 void pci_bar_print(struct pci_dev *dev, int bar_num) 223 { 224 phys_addr_t size, start, end; 225 uint32_t bar; 226 227 if (!pci_bar_is_valid(dev, bar_num)) 228 return; 229 230 bar = pci_bar_get(dev, bar_num); 231 size = pci_bar_size(dev, bar_num); 232 start = pci_bar_get_addr(dev, bar_num); 233 end = start + size - 1; 234 235 if (pci_bar_is64(dev, bar_num)) { 236 printf("BAR#%d,%d [%" PRIx64 "-%" PRIx64 " ", 237 bar_num, bar_num + 1, start, end); 238 } else { 239 printf("BAR#%d [%02x-%02x ", 240 bar_num, (uint32_t)start, (uint32_t)end); 241 } 242 243 if (bar & PCI_BASE_ADDRESS_SPACE_IO) { 244 printf("PIO"); 245 } else { 246 printf("MEM"); 247 switch (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) { 248 case PCI_BASE_ADDRESS_MEM_TYPE_32: 249 printf("32"); 250 break; 251 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 252 printf("1M"); 253 break; 254 case PCI_BASE_ADDRESS_MEM_TYPE_64: 255 printf("64"); 256 break; 257 default: 258 assert(0); 259 } 260 } 261 262 if (bar & PCI_BASE_ADDRESS_MEM_PREFETCH) 263 printf("/p"); 264 265 printf("]"); 266 } 267 268 void pci_dev_print_id(struct pci_dev *dev) 269 { 270 pcidevaddr_t bdf = dev->bdf; 271 272 printf("00.%02x.%1x %04x:%04x", bdf / 8, bdf % 8, 273 pci_config_readw(bdf, PCI_VENDOR_ID), 274 pci_config_readw(bdf, PCI_DEVICE_ID)); 275 } 276 277 static void pci_cap_print(struct pci_dev *dev, int cap_offset, int cap_id) 278 { 279 switch (cap_id) { 280 case PCI_CAP_ID_MSI: { 281 uint16_t control = pci_config_readw(dev->bdf, cap_offset + PCI_MSI_FLAGS); 282 printf("\tMSI,%s-bit capability ", control & PCI_MSI_FLAGS_64BIT ? "64" : "32"); 283 break; 284 } 285 default: 286 printf("\tcapability 0x%02x ", cap_id); 287 break; 288 } 289 printf("at offset 0x%02x\n", cap_offset); 290 } 291 292 void pci_dev_print(struct pci_dev *dev) 293 { 294 pcidevaddr_t bdf = dev->bdf; 295 uint8_t header = pci_config_readb(bdf, PCI_HEADER_TYPE); 296 uint8_t progif = pci_config_readb(bdf, PCI_CLASS_PROG); 297 uint8_t subclass = pci_config_readb(bdf, PCI_CLASS_DEVICE); 298 uint8_t class = pci_config_readb(bdf, PCI_CLASS_DEVICE + 1); 299 int i; 300 301 pci_dev_print_id(dev); 302 printf(" type %02x progif %02x class %02x subclass %02x\n", 303 header, progif, class, subclass); 304 305 pci_cap_walk(dev, pci_cap_print); 306 307 if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL) 308 return; 309 310 for (i = 0; i < PCI_BAR_NUM; i++) { 311 if (pci_bar_is_valid(dev, i)) { 312 printf("\t"); 313 pci_bar_print(dev, i); 314 printf("\n"); 315 } 316 if (pci_bar_is64(dev, i)) 317 i++; 318 } 319 } 320 321 void pci_print(void) 322 { 323 pcidevaddr_t devfn; 324 struct pci_dev pci_dev; 325 326 for (devfn = 0; devfn < PCI_DEVFN_MAX; ++devfn) { 327 if (pci_dev_exists(devfn)) { 328 pci_dev_init(&pci_dev, devfn); 329 pci_dev_print(&pci_dev); 330 } 331 } 332 } 333 334 void pci_dev_init(struct pci_dev *dev, pcidevaddr_t bdf) 335 { 336 int i; 337 338 memset(dev, 0, sizeof(*dev)); 339 dev->bdf = bdf; 340 341 for (i = 0; i < PCI_BAR_NUM; i++) { 342 if (pci_bar_size(dev, i)) { 343 dev->resource[i] = __pci_bar_get_addr(dev, i); 344 if (pci_bar_is64(dev, i)) { 345 assert(i + 1 < PCI_BAR_NUM); 346 dev->resource[i + 1] = dev->resource[i]; 347 i++; 348 } 349 } else { 350 dev->resource[i] = INVALID_PHYS_ADDR; 351 } 352 } 353 } 354 355 uint8_t pci_intx_line(struct pci_dev *dev) 356 { 357 return pci_config_readb(dev->bdf, PCI_INTERRUPT_LINE); 358 } 359 360 static void pci_cap_setup(struct pci_dev *dev, int cap_offset, int cap_id) 361 { 362 switch (cap_id) { 363 case PCI_CAP_ID_MSI: 364 dev->msi_offset = cap_offset; 365 break; 366 } 367 } 368 369 void pci_enable_defaults(struct pci_dev *dev) 370 { 371 /* Enable device DMA operations */ 372 pci_cmd_set_clr(dev, PCI_COMMAND_MASTER, 0); 373 pci_cap_walk(dev, pci_cap_setup); 374 } 375