1 #ifndef _ASMARM64_PGTABLE_HWDEF_H_ 2 #define _ASMARM64_PGTABLE_HWDEF_H_ 3 /* 4 * From arch/arm64/include/asm/pgtable-hwdef.h 5 * arch/arm64/include/asm/memory.h 6 * 7 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. 10 */ 11 12 #define UL(x) _AC(x, UL) 13 14 #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 15 16 /* 17 * PGDIR_SHIFT determines the size a top-level page table entry can map 18 * (depending on the configuration, this level can be 0, 1 or 2). 19 */ 20 #define PGDIR_SHIFT ((PAGE_SHIFT - 3) * PGTABLE_LEVELS + 3) 21 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 22 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 23 #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 24 25 /* From include/asm-generic/pgtable-nopmd.h */ 26 #define PMD_SHIFT PGDIR_SHIFT 27 #define PTRS_PER_PMD 1 28 #define PMD_SIZE (UL(1) << PMD_SHIFT) 29 #define PMD_MASK (~(PMD_SIZE-1)) 30 31 /* 32 * Section address mask and size definitions. 33 */ 34 #define SECTION_SHIFT PMD_SHIFT 35 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 36 #define SECTION_MASK (~(SECTION_SIZE-1)) 37 38 /* 39 * Hardware page table definitions. 40 * 41 * Level 1 descriptor (PMD). 42 */ 43 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 44 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 45 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 46 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 47 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 48 49 /* 50 * Section 51 */ 52 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 53 #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 54 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 55 #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 56 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 57 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 58 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 59 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 60 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 61 62 /* 63 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 64 */ 65 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 66 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 67 68 /* 69 * Level 3 descriptor (PTE). 70 */ 71 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 72 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 73 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 74 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 75 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 76 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 77 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 78 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 79 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 80 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 81 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 82 83 /* 84 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 85 */ 86 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 87 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 88 89 /* 90 * Highest possible physical address supported. 91 */ 92 #define PHYS_MASK_SHIFT (48) 93 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 94 95 /* 96 * TCR flags. 97 */ 98 #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 99 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 100 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 101 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 102 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 103 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 104 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 105 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 106 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 107 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 108 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 109 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 110 #define TCR_TG0_4K (UL(0) << 14) 111 #define TCR_TG0_64K (UL(1) << 14) 112 #define TCR_TG0_16K (UL(2) << 14) 113 #define TCR_TG1_16K (UL(1) << 30) 114 #define TCR_TG1_4K (UL(2) << 30) 115 #define TCR_TG1_64K (UL(3) << 30) 116 #define TCR_ASID16 (UL(1) << 36) 117 #define TCR_TBI0 (UL(1) << 37) 118 119 /* 120 * Memory types available. 121 */ 122 #define MT_DEVICE_nGnRnE 0 /* noncached */ 123 #define MT_DEVICE_nGnRE 1 /* device */ 124 #define MT_DEVICE_GRE 2 125 #define MT_NORMAL_NC 3 /* writecombine */ 126 #define MT_NORMAL 4 127 128 #endif /* _ASMARM64_PGTABLE_HWDEF_H_ */ 129