1 #ifndef _ASMARM64_PGTABLE_HWDEF_H_ 2 #define _ASMARM64_PGTABLE_HWDEF_H_ 3 /* 4 * From arch/arm64/include/asm/pgtable-hwdef.h 5 * arch/arm64/include/asm/memory.h 6 * 7 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. 10 */ 11 12 #include <asm/page.h> 13 14 #define UL(x) _AC(x, UL) 15 16 /* 17 * The number of bits a given page table level, n (where n=0 is the top), 18 * maps is ((max_n - n) - 1) * nr_bits_per_level + PAGE_SHIFT. Since a page 19 * table descriptor is 8 bytes we have (PAGE_SHIFT - 3) bits per level. We 20 * also have a maximum of 4 page table levels. Hence, 21 */ 22 #define PGTABLE_LEVEL_SHIFT(n) \ 23 (((4 - (n)) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT) 24 #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 25 26 #if PGTABLE_LEVELS > 2 27 #define PMD_SHIFT PGTABLE_LEVEL_SHIFT(2) 28 #define PTRS_PER_PMD PTRS_PER_PTE 29 #define PMD_SIZE (UL(1) << PMD_SHIFT) 30 #define PMD_MASK (~(PMD_SIZE-1)) 31 #else 32 #define PMD_SIZE PGDIR_SIZE 33 #define PMD_MASK PGDIR_MASK 34 #endif 35 36 #if PGTABLE_LEVELS > 3 37 #define PUD_SHIFT PGTABLE_LEVEL_SHIFT(1) 38 #define PTRS_PER_PUD PTRS_PER_PTE 39 #define PUD_SIZE (UL(1) << PUD_SHIFT) 40 #define PUD_MASK (~(PUD_SIZE-1)) 41 #else 42 #define PUD_SIZE PGDIR_SIZE 43 #define PUD_MASK PGDIR_MASK 44 #endif 45 46 #define PUD_VALID (_AT(pudval_t, 1) << 0) 47 48 /* 49 * PGDIR_SHIFT determines the size a top-level page table entry can map 50 * (depending on the configuration, this level can be 0, 1 or 2). 51 */ 52 #define PGDIR_SHIFT PGTABLE_LEVEL_SHIFT(4 - PGTABLE_LEVELS) 53 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 54 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 55 #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 56 57 #define PGD_VALID (_AT(pgdval_t, 1) << 0) 58 59 /* 60 * Section address mask and size definitions. 61 */ 62 #define SECTION_SHIFT PMD_SHIFT 63 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 64 #define SECTION_MASK (~(SECTION_SIZE-1)) 65 66 /* 67 * Hardware page table definitions. 68 * 69 * Level 0,1,2 descriptor (PGD, PUD and PMD). 70 */ 71 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 72 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 73 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 74 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 75 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 76 77 /* 78 * Section 79 */ 80 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 81 #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 82 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 83 #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 84 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 85 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 86 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 87 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 88 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 89 90 /* 91 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 92 */ 93 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 94 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 95 96 /* 97 * Level 3 descriptor (PTE). 98 */ 99 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 100 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 101 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 102 #define PTE_VALID (_AT(pteval_t, 1) << 0) 103 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 104 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 105 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 106 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 107 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 108 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 109 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 110 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 111 112 /* 113 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 114 */ 115 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 116 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 117 118 /* 119 * Highest possible physical address supported. 120 */ 121 #define PHYS_MASK_SHIFT (48) 122 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 123 124 /* 125 * TCR flags. 126 */ 127 #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 128 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 129 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 130 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 131 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 132 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 133 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 134 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 135 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 136 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 137 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 138 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 139 #define TCR_EPD1 (UL(1) << 23) 140 #define TCR_TG0_4K (UL(0) << 14) 141 #define TCR_TG0_64K (UL(1) << 14) 142 #define TCR_TG0_16K (UL(2) << 14) 143 #define TCR_TG1_16K (UL(1) << 30) 144 #define TCR_TG1_4K (UL(2) << 30) 145 #define TCR_TG1_64K (UL(3) << 30) 146 #define TCR_ASID16 (UL(1) << 36) 147 #define TCR_TBI0 (UL(1) << 37) 148 #define TCR_TBI1 (UL(1) << 38) 149 #define TCR_TCMA0 (UL(1) << 57) 150 151 /* 152 * Memory types available. 153 */ 154 #define MT_DEVICE_nGnRnE 0 /* noncached */ 155 #define MT_DEVICE_nGnRE 1 /* device */ 156 #define MT_DEVICE_GRE 2 157 #define MT_NORMAL_NC 3 /* writecombine */ 158 #define MT_NORMAL 4 159 #define MT_NORMAL_WT 5 160 #define MT_DEVICE_nGRE 6 161 #define MT_NORMAL_TAGGED 7 162 163 #endif /* _ASMARM64_PGTABLE_HWDEF_H_ */ 164