1 #ifndef _ASMARM64_PGTABLE_HWDEF_H_ 2 #define _ASMARM64_PGTABLE_HWDEF_H_ 3 /* 4 * From arch/arm64/include/asm/pgtable-hwdef.h 5 * arch/arm64/include/asm/memory.h 6 */ 7 #define UL(x) _AC(x, UL) 8 9 #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 10 11 /* 12 * PGDIR_SHIFT determines the size a top-level page table entry can map 13 * (depending on the configuration, this level can be 0, 1 or 2). 14 */ 15 #define PGDIR_SHIFT ((PAGE_SHIFT - 3) * PGTABLE_LEVELS + 3) 16 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 17 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 18 #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 19 20 /* From include/asm-generic/pgtable-nopud.h */ 21 #define PUD_SHIFT PGDIR_SHIFT 22 #define PTRS_PER_PUD 1 23 #define PUD_SIZE (UL(1) << PUD_SHIFT) 24 #define PUD_MASK (~(PUD_SIZE-1)) 25 /* From include/asm-generic/pgtable-nopmd.h */ 26 #define PMD_SHIFT PUD_SHIFT 27 #define PTRS_PER_PMD 1 28 #define PMD_SIZE (UL(1) << PMD_SHIFT) 29 #define PMD_MASK (~(PMD_SIZE-1)) 30 31 /* 32 * Section address mask and size definitions. 33 */ 34 #define SECTION_SHIFT PMD_SHIFT 35 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 36 #define SECTION_MASK (~(SECTION_SIZE-1)) 37 38 /* 39 * Hardware page table definitions. 40 * 41 * Level 1 descriptor (PUD). 42 */ 43 #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 44 #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 45 #define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 46 #define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0) 47 48 /* 49 * Level 2 descriptor (PMD). 50 */ 51 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 52 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 53 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 54 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 55 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 56 57 /* 58 * Section 59 */ 60 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 61 #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 62 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 63 #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 64 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 65 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 66 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 67 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 68 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 69 70 /* 71 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 72 */ 73 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 74 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 75 76 /* 77 * Level 3 descriptor (PTE). 78 */ 79 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 80 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 81 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 82 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 83 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 84 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 85 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 86 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 87 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 88 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 89 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 90 91 /* 92 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 93 */ 94 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 95 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 96 97 /* 98 * Highest possible physical address supported. 99 */ 100 #define PHYS_MASK_SHIFT (48) 101 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 102 103 /* 104 * TCR flags. 105 */ 106 #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 107 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 108 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 109 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 110 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 111 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 112 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 113 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 114 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 115 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 116 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 117 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 118 #define TCR_TG0_4K (UL(0) << 14) 119 #define TCR_TG0_64K (UL(1) << 14) 120 #define TCR_TG0_16K (UL(2) << 14) 121 #define TCR_TG1_16K (UL(1) << 30) 122 #define TCR_TG1_4K (UL(2) << 30) 123 #define TCR_TG1_64K (UL(3) << 30) 124 #define TCR_ASID16 (UL(1) << 36) 125 #define TCR_TBI0 (UL(1) << 37) 126 127 /* 128 * Memory types available. 129 */ 130 #define MT_DEVICE_nGnRnE 0 /* noncached */ 131 #define MT_DEVICE_nGnRE 1 /* device */ 132 #define MT_DEVICE_GRE 2 133 #define MT_NORMAL_NC 3 /* writecombine */ 134 #define MT_NORMAL 4 135 136 #endif /* _ASMARM64_PGTABLE_HWDEF_H_ */ 137