1 #ifndef _ASMARM64_PGTABLE_HWDEF_H_ 2 #define _ASMARM64_PGTABLE_HWDEF_H_ 3 /* 4 * From arch/arm64/include/asm/pgtable-hwdef.h 5 * arch/arm64/include/asm/memory.h 6 * 7 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. 10 */ 11 12 #define UL(x) _AC(x, UL) 13 14 #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 15 16 /* 17 * PGDIR_SHIFT determines the size a top-level page table entry can map 18 * (depending on the configuration, this level can be 0, 1 or 2). 19 */ 20 #define PGDIR_SHIFT ((PAGE_SHIFT - 3) * PGTABLE_LEVELS + 3) 21 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 22 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 23 #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 24 25 /* From include/asm-generic/pgtable-nopud.h */ 26 #define PUD_SHIFT PGDIR_SHIFT 27 #define PTRS_PER_PUD 1 28 #define PUD_SIZE (UL(1) << PUD_SHIFT) 29 #define PUD_MASK (~(PUD_SIZE-1)) 30 /* From include/asm-generic/pgtable-nopmd.h */ 31 #define PMD_SHIFT PUD_SHIFT 32 #define PTRS_PER_PMD 1 33 #define PMD_SIZE (UL(1) << PMD_SHIFT) 34 #define PMD_MASK (~(PMD_SIZE-1)) 35 36 /* 37 * Section address mask and size definitions. 38 */ 39 #define SECTION_SHIFT PMD_SHIFT 40 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 41 #define SECTION_MASK (~(SECTION_SIZE-1)) 42 43 /* 44 * Hardware page table definitions. 45 * 46 * Level 1 descriptor (PUD). 47 */ 48 #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 49 #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 50 #define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 51 #define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0) 52 53 /* 54 * Level 2 descriptor (PMD). 55 */ 56 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 57 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 58 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 59 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 60 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 61 62 /* 63 * Section 64 */ 65 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 66 #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 67 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 68 #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 69 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 70 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 71 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 72 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 73 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 74 75 /* 76 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 77 */ 78 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 79 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 80 81 /* 82 * Level 3 descriptor (PTE). 83 */ 84 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 85 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 86 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 87 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 88 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 89 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 90 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 91 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 92 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 93 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 94 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 95 96 /* 97 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 98 */ 99 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 100 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 101 102 /* 103 * Highest possible physical address supported. 104 */ 105 #define PHYS_MASK_SHIFT (48) 106 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 107 108 /* 109 * TCR flags. 110 */ 111 #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 112 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 113 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 114 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 115 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 116 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 117 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 118 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 119 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 120 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 121 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 122 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 123 #define TCR_TG0_4K (UL(0) << 14) 124 #define TCR_TG0_64K (UL(1) << 14) 125 #define TCR_TG0_16K (UL(2) << 14) 126 #define TCR_TG1_16K (UL(1) << 30) 127 #define TCR_TG1_4K (UL(2) << 30) 128 #define TCR_TG1_64K (UL(3) << 30) 129 #define TCR_ASID16 (UL(1) << 36) 130 #define TCR_TBI0 (UL(1) << 37) 131 132 /* 133 * Memory types available. 134 */ 135 #define MT_DEVICE_nGnRnE 0 /* noncached */ 136 #define MT_DEVICE_nGnRE 1 /* device */ 137 #define MT_DEVICE_GRE 2 138 #define MT_NORMAL_NC 3 /* writecombine */ 139 #define MT_NORMAL 4 140 141 #endif /* _ASMARM64_PGTABLE_HWDEF_H_ */ 142