xref: /kvm-unit-tests/lib/arm/asm/processor.h (revision 410b3bf09e76fd2b6d68b424a26d407a0bc4bc11)
1 #ifndef _ASMARM_PROCESSOR_H_
2 #define _ASMARM_PROCESSOR_H_
3 /*
4  * Copyright (C) 2014, Red Hat Inc, Andrew Jones <drjones@redhat.com>
5  *
6  * This work is licensed under the terms of the GNU LGPL, version 2.
7  */
8 #include <asm/ptrace.h>
9 #include <asm/sysreg.h>
10 #include <asm/barrier.h>
11 
12 #define CTR_DMINLINE_SHIFT	16
13 #define CTR_DMINLINE_MASK	(0xf << 16)
14 #define CTR_DMINLINE(x)	\
15 	(((x) & CTR_DMINLINE_MASK) >> CTR_DMINLINE_SHIFT)
16 
17 enum vector {
18 	EXCPTN_RST,
19 	EXCPTN_UND,
20 	EXCPTN_SVC,
21 	EXCPTN_PABT,
22 	EXCPTN_DABT,
23 	EXCPTN_ADDREXCPTN,
24 	EXCPTN_IRQ,
25 	EXCPTN_FIQ,
26 	EXCPTN_MAX,
27 };
28 
29 typedef void (*exception_fn)(struct pt_regs *);
30 extern void install_exception_handler(enum vector v, exception_fn fn);
31 
32 extern void show_regs(struct pt_regs *regs);
33 
34 static inline unsigned long current_cpsr(void)
35 {
36 	unsigned long cpsr;
37 	asm volatile("mrs %0, cpsr" : "=r" (cpsr));
38 	return cpsr;
39 }
40 
41 #define current_mode() (current_cpsr() & MODE_MASK)
42 
43 static inline void local_irq_enable(void)
44 {
45 	asm volatile("cpsie i" : : : "memory", "cc");
46 }
47 
48 static inline void local_irq_disable(void)
49 {
50 	asm volatile("cpsid i" : : : "memory", "cc");
51 }
52 
53 #define MPIDR __ACCESS_CP15(c0, 0, c0, 5)
54 static inline uint64_t get_mpidr(void)
55 {
56 	return read_sysreg(MPIDR);
57 }
58 
59 #define MPIDR_HWID_BITMASK 0xffffff
60 extern int mpidr_to_cpu(uint64_t mpidr);
61 
62 #define MPIDR_LEVEL_SHIFT(level) \
63 	(((1 << level) >> 1) << 3)
64 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
65 	((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff)
66 
67 extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr);
68 extern bool is_user(void);
69 
70 #define CNTVCT		__ACCESS_CP15_64(1, c14)
71 #define CNTFRQ		__ACCESS_CP15(c14, 0, c0, 0)
72 #define CTR		__ACCESS_CP15(c0, 0, c0, 1)
73 
74 static inline u64 get_cntvct(void)
75 {
76 	isb();
77 	return read_sysreg(CNTVCT);
78 }
79 
80 static inline u32 get_cntfrq(void)
81 {
82 	return read_sysreg(CNTFRQ);
83 }
84 
85 static inline u32 get_ctr(void)
86 {
87 	return read_sysreg(CTR);
88 }
89 
90 extern u32 dcache_line_size;
91 
92 #endif /* _ASMARM_PROCESSOR_H_ */
93