1 #ifndef _ASMARM_PGTABLE_HWDEF_H_ 2 #define _ASMARM_PGTABLE_HWDEF_H_ 3 /* 4 * From arch/arm/include/asm/pgtable-3level.h 5 * arch/arm/include/asm/pgtable-3level-hwdef.h 6 * 7 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. 10 */ 11 12 #define PTRS_PER_PGD 4 13 #define PGDIR_SHIFT 30 14 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 15 #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1)) 16 17 #define PGD_VALID (_AT(pgdval_t, 1) << 0) 18 19 #define PTRS_PER_PTE 512 20 #define PTRS_PER_PMD 512 21 22 #define PMD_SHIFT 21 23 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 24 #define PMD_MASK (~((1 << PMD_SHIFT) - 1)) 25 26 #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 27 28 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 29 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ 30 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 31 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 32 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 33 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 34 35 /* 36 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 37 */ 38 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 39 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 40 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 41 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 42 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 43 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 44 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 45 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 46 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 47 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 48 49 /* 50 * Hardware page table definitions. 51 * 52 * + Level 1/2 descriptor 53 * - common 54 */ 55 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 56 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 57 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 58 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 59 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 60 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 61 #define PMD_BIT4 (_AT(pmdval_t, 0)) 62 #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 63 #define PMD_APTABLE_SHIFT (61) 64 #define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) 65 #define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) 66 67 /* 68 * - section 69 */ 70 #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 71 #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 72 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 73 #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ 74 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 75 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 76 #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 77 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 78 #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 79 #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 80 #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 81 #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) 82 #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 83 84 /* 85 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 86 */ 87 #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ 88 #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ 89 #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ 90 #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ 91 #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ 92 93 /* 94 * + Level 3 descriptor (PTE) 95 */ 96 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 97 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 98 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 99 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 100 #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 101 #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 102 #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ 103 #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 104 #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 105 #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ 106 #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ 107 108 /* 109 * 40-bit physical address supported. 110 */ 111 #define PHYS_MASK_SHIFT (40) 112 #define PHYS_MASK ((_AC(1, ULL) << PHYS_MASK_SHIFT) - 1) 113 114 #define TTBCR_IRGN0_WBWA (_AC(1, UL) << 8) 115 #define TTBCR_ORGN0_WBWA (_AC(1, UL) << 10) 116 #define TTBCR_SH0_SHARED (_AC(3, UL) << 12) 117 #define TTBCR_IRGN1_WBWA (_AC(1, UL) << 24) 118 #define TTBCR_ORGN1_WBWA (_AC(1, UL) << 26) 119 #define TTBCR_SH1_SHARED (_AC(3, UL) << 28) 120 #define TTBCR_EAE (_AC(1, UL) << 31) 121 122 #endif /* _ASMARM_PGTABLE_HWDEF_H_ */ 123