1 #ifndef _ASMARM_PGTABLE_HWDEF_H_ 2 #define _ASMARM_PGTABLE_HWDEF_H_ 3 /* 4 * From arch/arm/include/asm/pgtable-3level.h 5 * arch/arm/include/asm/pgtable-3level-hwdef.h 6 */ 7 8 #define PTRS_PER_PGD 4 9 #define PGDIR_SHIFT 30 10 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 11 #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1)) 12 13 #define PTRS_PER_PTE 512 14 #define PTRS_PER_PMD 512 15 16 #define PMD_SHIFT 21 17 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 18 #define PMD_MASK (~((1 << PMD_SHIFT) - 1)) 19 20 #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 21 22 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 23 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ 24 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 25 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 26 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 27 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 28 29 /* 30 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 31 */ 32 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 33 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 34 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 35 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 36 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 37 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 38 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 39 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 40 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 41 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 42 43 /* 44 * Hardware page table definitions. 45 * 46 * + Level 1/2 descriptor 47 * - common 48 */ 49 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 50 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 51 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 52 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 53 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 54 #define PMD_BIT4 (_AT(pmdval_t, 0)) 55 #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 56 #define PMD_APTABLE_SHIFT (61) 57 #define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) 58 #define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) 59 60 /* 61 * - section 62 */ 63 #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 64 #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 65 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 66 #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ 67 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 68 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 69 #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 70 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 71 #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 72 #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 73 #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 74 #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) 75 #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 76 77 /* 78 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 79 */ 80 #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ 81 #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ 82 #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ 83 #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ 84 #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ 85 86 /* 87 * + Level 3 descriptor (PTE) 88 */ 89 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 90 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 91 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 92 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 93 #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 94 #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 95 #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ 96 #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 97 #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 98 #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ 99 #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ 100 101 /* 102 * 40-bit physical address supported. 103 */ 104 #define PHYS_MASK_SHIFT (40) 105 #define PHYS_MASK ((_AC(1, ULL) << PHYS_MASK_SHIFT) - 1) 106 107 #endif /* _ASMARM_PGTABLE_HWDEF_H_ */ 108