17a693feeSAndrew Jones #ifndef _ASMARM_PGTABLE_HWDEF_H_ 27a693feeSAndrew Jones #define _ASMARM_PGTABLE_HWDEF_H_ 37a693feeSAndrew Jones /* 4*a796123fSAndrew Jones * From arch/arm/include/asm/pgtable-3level.h 5*a796123fSAndrew Jones * arch/arm/include/asm/pgtable-3level-hwdef.h 67a693feeSAndrew Jones */ 77a693feeSAndrew Jones 8*a796123fSAndrew Jones #define PTRS_PER_PGD 4 9*a796123fSAndrew Jones #define PGDIR_SHIFT 30 10*a796123fSAndrew Jones #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 11*a796123fSAndrew Jones #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1)) 12*a796123fSAndrew Jones 13*a796123fSAndrew Jones #define PTRS_PER_PTE 512 14*a796123fSAndrew Jones #define PTRS_PER_PMD 512 15*a796123fSAndrew Jones 16*a796123fSAndrew Jones #define PMD_SHIFT 21 17*a796123fSAndrew Jones #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 18*a796123fSAndrew Jones #define PMD_MASK (~((1 << PMD_SHIFT) - 1)) 19*a796123fSAndrew Jones 20*a796123fSAndrew Jones #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 21*a796123fSAndrew Jones 22*a796123fSAndrew Jones #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 23*a796123fSAndrew Jones #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ 24*a796123fSAndrew Jones #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 25*a796123fSAndrew Jones #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 26*a796123fSAndrew Jones #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 27*a796123fSAndrew Jones #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 28*a796123fSAndrew Jones 29*a796123fSAndrew Jones /* 30*a796123fSAndrew Jones * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 31*a796123fSAndrew Jones */ 32*a796123fSAndrew Jones #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 33*a796123fSAndrew Jones #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 34*a796123fSAndrew Jones #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 35*a796123fSAndrew Jones #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 36*a796123fSAndrew Jones #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 37*a796123fSAndrew Jones #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 38*a796123fSAndrew Jones #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 39*a796123fSAndrew Jones #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 40*a796123fSAndrew Jones #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 41*a796123fSAndrew Jones #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 42*a796123fSAndrew Jones 437a693feeSAndrew Jones /* 447a693feeSAndrew Jones * Hardware page table definitions. 457a693feeSAndrew Jones * 467a693feeSAndrew Jones * + Level 1/2 descriptor 477a693feeSAndrew Jones * - common 487a693feeSAndrew Jones */ 497a693feeSAndrew Jones #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 507a693feeSAndrew Jones #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 517a693feeSAndrew Jones #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 527a693feeSAndrew Jones #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 537a693feeSAndrew Jones #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 547a693feeSAndrew Jones #define PMD_BIT4 (_AT(pmdval_t, 0)) 557a693feeSAndrew Jones #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 567a693feeSAndrew Jones #define PMD_APTABLE_SHIFT (61) 577a693feeSAndrew Jones #define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) 587a693feeSAndrew Jones #define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) 597a693feeSAndrew Jones 607a693feeSAndrew Jones /* 617a693feeSAndrew Jones * - section 627a693feeSAndrew Jones */ 637a693feeSAndrew Jones #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 647a693feeSAndrew Jones #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 657a693feeSAndrew Jones #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 667a693feeSAndrew Jones #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ 677a693feeSAndrew Jones #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 687a693feeSAndrew Jones #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 697a693feeSAndrew Jones #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 707a693feeSAndrew Jones #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 717a693feeSAndrew Jones #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 727a693feeSAndrew Jones #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 737a693feeSAndrew Jones #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 747a693feeSAndrew Jones #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) 757a693feeSAndrew Jones #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 767a693feeSAndrew Jones 777a693feeSAndrew Jones /* 787a693feeSAndrew Jones * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 797a693feeSAndrew Jones */ 807a693feeSAndrew Jones #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ 817a693feeSAndrew Jones #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ 827a693feeSAndrew Jones #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ 837a693feeSAndrew Jones #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ 847a693feeSAndrew Jones #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ 857a693feeSAndrew Jones 867a693feeSAndrew Jones /* 877a693feeSAndrew Jones * + Level 3 descriptor (PTE) 887a693feeSAndrew Jones */ 897a693feeSAndrew Jones #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 907a693feeSAndrew Jones #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 917a693feeSAndrew Jones #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 927a693feeSAndrew Jones #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 937a693feeSAndrew Jones #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 947a693feeSAndrew Jones #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 957a693feeSAndrew Jones #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ 967a693feeSAndrew Jones #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 977a693feeSAndrew Jones #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 987a693feeSAndrew Jones #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ 997a693feeSAndrew Jones #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ 1007a693feeSAndrew Jones 10162e6e986SAndrew Jones /* 10262e6e986SAndrew Jones * 40-bit physical address supported. 10362e6e986SAndrew Jones */ 10462e6e986SAndrew Jones #define PHYS_MASK_SHIFT (40) 10562e6e986SAndrew Jones #define PHYS_MASK ((_AC(1, ULL) << PHYS_MASK_SHIFT) - 1) 10662e6e986SAndrew Jones 1077a693feeSAndrew Jones #endif /* _ASMARM_PGTABLE_HWDEF_H_ */ 108