17a693feeSAndrew Jones #ifndef _ASMARM_PGTABLE_HWDEF_H_ 27a693feeSAndrew Jones #define _ASMARM_PGTABLE_HWDEF_H_ 37a693feeSAndrew Jones /* 4a796123fSAndrew Jones * From arch/arm/include/asm/pgtable-3level.h 5a796123fSAndrew Jones * arch/arm/include/asm/pgtable-3level-hwdef.h 649f758b8SAndrew Jones * 749f758b8SAndrew Jones * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 849f758b8SAndrew Jones * 949f758b8SAndrew Jones * This work is licensed under the terms of the GNU GPL, version 2. 107a693feeSAndrew Jones */ 117a693feeSAndrew Jones 12a796123fSAndrew Jones #define PTRS_PER_PGD 4 13a796123fSAndrew Jones #define PGDIR_SHIFT 30 14a796123fSAndrew Jones #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 15a796123fSAndrew Jones #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1)) 16a796123fSAndrew Jones 1702f1cdc8SAlexandru Elisei #define PGD_VALID (_AT(pgdval_t, 1) << 0) 1802f1cdc8SAlexandru Elisei 19a796123fSAndrew Jones #define PTRS_PER_PTE 512 20a796123fSAndrew Jones #define PTRS_PER_PMD 512 21a796123fSAndrew Jones 22a2d06852SNikos Nikoleris /* For compatibility with arm64 page tables */ 23a2d06852SNikos Nikoleris #define PUD_SIZE PGDIR_SIZE 24a2d06852SNikos Nikoleris #define PUD_MASK PGDIR_MASK 25a2d06852SNikos Nikoleris 26a796123fSAndrew Jones #define PMD_SHIFT 21 27a796123fSAndrew Jones #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 28a796123fSAndrew Jones #define PMD_MASK (~((1 << PMD_SHIFT) - 1)) 29a796123fSAndrew Jones 30a796123fSAndrew Jones #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 31a796123fSAndrew Jones 32a796123fSAndrew Jones #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 33a796123fSAndrew Jones #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ 34a796123fSAndrew Jones #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 35a796123fSAndrew Jones #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 36a796123fSAndrew Jones #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 37*e97e1c82SAndrew Jones #define L_PTE_PXN (_AT(pteval_t, 1) << 53) /* PXN */ 38a796123fSAndrew Jones #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 39a796123fSAndrew Jones 40a796123fSAndrew Jones /* 41a796123fSAndrew Jones * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 42a796123fSAndrew Jones */ 43a796123fSAndrew Jones #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 44a796123fSAndrew Jones #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 45a796123fSAndrew Jones #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 46a796123fSAndrew Jones #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 47a796123fSAndrew Jones #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 48a796123fSAndrew Jones #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 49a796123fSAndrew Jones #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 50a796123fSAndrew Jones #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 51a796123fSAndrew Jones #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 52a796123fSAndrew Jones #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 53a796123fSAndrew Jones 547a693feeSAndrew Jones /* 557a693feeSAndrew Jones * Hardware page table definitions. 567a693feeSAndrew Jones * 577a693feeSAndrew Jones * + Level 1/2 descriptor 587a693feeSAndrew Jones * - common 597a693feeSAndrew Jones */ 607a693feeSAndrew Jones #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 617a693feeSAndrew Jones #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 627a693feeSAndrew Jones #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 637a693feeSAndrew Jones #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 6402f1cdc8SAlexandru Elisei #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 657a693feeSAndrew Jones #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 667a693feeSAndrew Jones #define PMD_BIT4 (_AT(pmdval_t, 0)) 677a693feeSAndrew Jones #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 687a693feeSAndrew Jones #define PMD_APTABLE_SHIFT (61) 697a693feeSAndrew Jones #define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) 707a693feeSAndrew Jones #define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) 717a693feeSAndrew Jones 727a693feeSAndrew Jones /* 737a693feeSAndrew Jones * - section 747a693feeSAndrew Jones */ 757a693feeSAndrew Jones #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 767a693feeSAndrew Jones #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 777a693feeSAndrew Jones #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 787a693feeSAndrew Jones #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ 797a693feeSAndrew Jones #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 807a693feeSAndrew Jones #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 817a693feeSAndrew Jones #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 827a693feeSAndrew Jones #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 837a693feeSAndrew Jones #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 847a693feeSAndrew Jones #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 857a693feeSAndrew Jones #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 867a693feeSAndrew Jones #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) 877a693feeSAndrew Jones #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 887a693feeSAndrew Jones 897a693feeSAndrew Jones /* 907a693feeSAndrew Jones * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 917a693feeSAndrew Jones */ 927a693feeSAndrew Jones #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ 937a693feeSAndrew Jones #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ 947a693feeSAndrew Jones #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ 957a693feeSAndrew Jones #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ 967a693feeSAndrew Jones #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ 977a693feeSAndrew Jones 987a693feeSAndrew Jones /* 997a693feeSAndrew Jones * + Level 3 descriptor (PTE) 1007a693feeSAndrew Jones */ 1017a693feeSAndrew Jones #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 1027a693feeSAndrew Jones #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 1037a693feeSAndrew Jones #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 1047a693feeSAndrew Jones #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 1057a693feeSAndrew Jones #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 1067a693feeSAndrew Jones #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 1077a693feeSAndrew Jones #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ 1087a693feeSAndrew Jones #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 1097a693feeSAndrew Jones #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 1107a693feeSAndrew Jones #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ 1117a693feeSAndrew Jones #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ 1127a693feeSAndrew Jones 11362e6e986SAndrew Jones /* 11462e6e986SAndrew Jones * 40-bit physical address supported. 11562e6e986SAndrew Jones */ 11662e6e986SAndrew Jones #define PHYS_MASK_SHIFT (40) 11762e6e986SAndrew Jones #define PHYS_MASK ((_AC(1, ULL) << PHYS_MASK_SHIFT) - 1) 11862e6e986SAndrew Jones 11920239febSAlexandru Elisei #define TTBCR_IRGN0_WBWA (_AC(1, UL) << 8) 12020239febSAlexandru Elisei #define TTBCR_ORGN0_WBWA (_AC(1, UL) << 10) 12120239febSAlexandru Elisei #define TTBCR_SH0_SHARED (_AC(3, UL) << 12) 12220239febSAlexandru Elisei #define TTBCR_IRGN1_WBWA (_AC(1, UL) << 24) 12320239febSAlexandru Elisei #define TTBCR_ORGN1_WBWA (_AC(1, UL) << 26) 12420239febSAlexandru Elisei #define TTBCR_SH1_SHARED (_AC(3, UL) << 28) 12520239febSAlexandru Elisei #define TTBCR_EAE (_AC(1, UL) << 31) 12620239febSAlexandru Elisei 1277a693feeSAndrew Jones #endif /* _ASMARM_PGTABLE_HWDEF_H_ */ 128