1 /* 2 * All GIC* defines are lifted from include/linux/irqchip/arm-gic-v3.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM_GIC_V3_H_ 9 #define _ASMARM_GIC_V3_H_ 10 11 #ifndef _ASMARM_GIC_H_ 12 #error Do not directly include <asm/gic-v3.h>. Include <asm/gic.h> 13 #endif 14 15 /* 16 * Distributor registers 17 * 18 * We expect to be run in Non-secure mode, thus we define the 19 * group1 enable bits with respect to that view. 20 */ 21 #define GICD_CTLR_RWP (1U << 31) 22 #define GICD_CTLR_ARE_NS (1U << 4) 23 #define GICD_CTLR_ENABLE_G1A (1U << 1) 24 #define GICD_CTLR_ENABLE_G1 (1U << 0) 25 26 /* Re-Distributor registers, offsets from RD_base */ 27 #define GICR_TYPER 0x0008 28 29 #define GICR_TYPER_LAST (1U << 4) 30 31 /* Re-Distributor registers, offsets from SGI_base */ 32 #define GICR_IGROUPR0 GICD_IGROUPR 33 #define GICR_ISENABLER0 GICD_ISENABLER 34 #define GICR_ICENABLER0 GICD_ICENABLER 35 #define GICR_ISPENDR0 GICD_ISPENDR 36 #define GICR_ICPENDR0 GICD_ICPENDR 37 #define GICR_ISACTIVER0 GICD_ISACTIVER 38 #define GICR_ICACTIVER0 GICD_ICACTIVER 39 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 40 41 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 42 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 43 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 44 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 45 (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT) 46 47 #include <asm/arch_gicv3.h> 48 49 #ifndef __ASSEMBLY__ 50 #include <asm/setup.h> 51 #include <asm/processor.h> 52 #include <asm/delay.h> 53 #include <asm/cpumask.h> 54 #include <asm/smp.h> 55 #include <asm/io.h> 56 57 #define GICV3_NR_REDISTS 8 58 59 struct gicv3_data { 60 void *dist_base; 61 void *redist_bases[GICV3_NR_REDISTS]; 62 void *redist_base[NR_CPUS]; 63 unsigned int irq_nr; 64 }; 65 extern struct gicv3_data gicv3_data; 66 67 #define gicv3_dist_base() (gicv3_data.dist_base) 68 #define gicv3_redist_base() (gicv3_data.redist_base[smp_processor_id()]) 69 #define gicv3_sgi_base() (gicv3_data.redist_base[smp_processor_id()] + SZ_64K) 70 71 extern int gicv3_init(void); 72 extern void gicv3_enable_defaults(void); 73 extern u32 gicv3_read_iar(void); 74 extern u32 gicv3_iar_irqnr(u32 iar); 75 extern void gicv3_write_eoir(u32 irqstat); 76 extern void gicv3_ipi_send_single(int irq, int cpu); 77 extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest); 78 extern void gicv3_set_redist_base(size_t stride); 79 80 static inline void gicv3_do_wait_for_rwp(void *base) 81 { 82 int count = 100000; /* 1s */ 83 84 while (readl(base + GICD_CTLR) & GICD_CTLR_RWP) { 85 if (!--count) { 86 printf("GICv3: RWP timeout!\n"); 87 abort(); 88 } 89 cpu_relax(); 90 udelay(10); 91 }; 92 } 93 94 static inline void gicv3_dist_wait_for_rwp(void) 95 { 96 gicv3_do_wait_for_rwp(gicv3_dist_base()); 97 } 98 99 static inline void gicv3_redist_wait_for_uwp(void) 100 { 101 /* 102 * We can build on gic_do_wait_for_rwp, which uses GICD_ registers 103 * because GICD_CTLR == GICR_CTLR and GICD_CTLR_RWP == GICR_CTLR_UWP 104 */ 105 gicv3_do_wait_for_rwp(gicv3_redist_base()); 106 } 107 108 static inline u32 mpidr_compress(u64 mpidr) 109 { 110 u64 compressed = mpidr & MPIDR_HWID_BITMASK; 111 112 compressed = (((compressed >> 32) & 0xff) << 24) | compressed; 113 return compressed; 114 } 115 116 static inline u64 mpidr_uncompress(u32 compressed) 117 { 118 u64 mpidr = ((u64)compressed >> 24) << 32; 119 120 mpidr |= compressed & MPIDR_HWID_BITMASK; 121 return mpidr; 122 } 123 124 #endif /* !__ASSEMBLY__ */ 125 #endif /* _ASMARM_GIC_V3_H_ */ 126