1 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. 2 // 3 // Portions Copyright 2017 The Chromium OS Authors. All rights reserved. 4 // Use of this source code is governed by a BSD-style license that can be 5 // found in the LICENSE-BSD-3-Clause file. 6 // 7 // Copyright © 2019 Intel Corporation 8 // 9 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 10 // 11 // Copyright © 2020, Microsoft Corporation 12 // 13 14 pub mod emulator; 15 pub mod gdt; 16 #[allow(non_upper_case_globals)] 17 #[allow(non_camel_case_types)] 18 #[allow(non_snake_case)] 19 #[allow(non_upper_case_globals)] 20 pub mod msr_index; 21 22 // MTRR constants 23 pub const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11 24 pub const MTRR_MEM_TYPE_WB: u64 = 0x6; 25 26 // IOAPIC pins 27 pub const NUM_IOAPIC_PINS: usize = 24; 28 29 // X86 Exceptions 30 #[allow(dead_code)] 31 #[derive(Clone, Debug)] 32 pub enum Exception { 33 DE = 0, // Divide Error 34 DB = 1, // Debug Exception 35 BP = 3, // Breakpoint 36 OF = 4, // Overflow 37 BR = 5, // BOUND Range Exceeded 38 UD = 6, // Invalid/Undefined Opcode 39 NM = 7, // No Math Coprocessor 40 DF = 8, // Double Fault 41 TS = 10, // Invalid TSS 42 NP = 11, // Segment Not Present 43 SS = 12, // Stack Segment Fault 44 GP = 13, // General Protection 45 PF = 14, // Page Fault 46 MF = 16, // Math Fault 47 AC = 17, // Alignment Check 48 MC = 18, // Machine Check 49 XM = 19, // SIMD Floating-Point Exception 50 VE = 20, // Virtualization Exception 51 CP = 21, // Control Protection Exception 52 } 53 54 pub mod regs; 55 56 // Abstracted segment register ops. 57 // Each x86 hypervisor should implement those. 58 pub trait SegmentRegisterOps { 59 // Segment type 60 fn segment_type(&self) -> u8; 61 fn set_segment_type(&mut self, val: u8); 62 63 // Descriptor Privilege Level (DPL) 64 fn dpl(&self) -> u8; 65 fn set_dpl(&mut self, val: u8); 66 67 // Granularity 68 fn granularity(&self) -> u8; 69 fn set_granularity(&mut self, val: u8); 70 71 // Memory Presence 72 fn present(&self) -> u8; 73 fn set_present(&mut self, val: u8); 74 75 // Long mode 76 fn long(&self) -> u8; 77 fn set_long(&mut self, val: u8); 78 79 // Available for system use (AVL) 80 fn avl(&self) -> u8; 81 fn set_avl(&mut self, val: u8); 82 83 // Descriptor type (System or code/data) 84 fn desc_type(&self) -> u8; 85 fn set_desc_type(&mut self, val: u8); 86 87 // D/B 88 fn db(&self) -> u8; 89 fn set_db(&mut self, val: u8); 90 } 91 92 // Code segment 93 pub const CODE_SEGMENT_TYPE: u8 = 0x8; 94 95 // Read/Write or Read/Exec segment 96 pub const RWRX_SEGMENT_TYPE: u8 = 0x2; 97 98 // Expand down segment 99 pub const EXPAND_DOWN_SEGMENT_TYPE: u8 = 0x4; 100 101 pub fn segment_type_code(t: u8) -> bool { 102 t & CODE_SEGMENT_TYPE != 0 103 } 104 105 pub fn segment_type_ro(t: u8) -> bool { 106 t & !RWRX_SEGMENT_TYPE == 0 107 } 108 109 pub fn segment_type_expand_down(t: u8) -> bool { 110 !segment_type_code(t) && (t & EXPAND_DOWN_SEGMENT_TYPE != 0) 111 } 112 #[macro_export] 113 macro_rules! msr { 114 ($msr:expr) => { 115 MsrEntry { 116 index: $msr, 117 data: 0x0, 118 ..Default::default() 119 } 120 }; 121 } 122 #[macro_export] 123 macro_rules! msr_data { 124 ($msr:expr, $data:expr) => { 125 MsrEntry { 126 index: $msr, 127 data: $data, 128 ..Default::default() 129 } 130 }; 131 } 132