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/src/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DPPCTargetParser.def114 PPC_LNX_FEATURE("4xxmac","4xx CPU has a Multiply Accumulator",PPCF_4XXMAC,0x02000000,PPC_FAWORD_HWC…
115 PPC_LNX_FEATURE("altivec","CPU has a SIMD/Vector Unit",PPCF_ALTIVEC,0x10000000,PPC_FAWORD_HWCAP)
116 PPC_LNX_FEATURE("arch_2_05","CPU supports ISA 205 (eg, POWER6)",PPCF_ARCH205,0x00001000,PPC_FAWORD_…
117 PPC_LNX_FEATURE("arch_2_06","CPU supports ISA 206 (eg, POWER7)",PPCF_ARCH206,0x00000100,PPC_FAWORD_…
118 PPC_LNX_FEATURE("arch_2_07","CPU supports ISA 207 (eg, POWER8)",PPCF_ARCH207,0x80000000,PPC_FAWORD_…
119 PPC_LNX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",PPCF_ARCH30,0x00800000,PPC_FAWORD_HW…
120 PPC_LNX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",PPCF_ARCH31,0x00040000,PPC_FAWORD_HW…
121 PPC_LNX_FEATURE("archpmu","CPU supports the set of compatible performance monitoring events",PPCF_A…
122 PPC_LNX_FEATURE("booke","CPU supports the Embedded ISA category",PPCF_BOOKE,0x00008000,PPC_FAWORD_H…
123 PPC_LNX_FEATURE("cellbe","CPU has a CELL broadband engine",PPCF_CELLBE,0x00010000,PPC_FAWORD_HWCAP)
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/src/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/
H A Dx86.c381 const char *CPU = 0; in getIntelProcessorTypeAndSubtype() local
393 CPU = "core2"; in getIntelProcessorTypeAndSubtype()
402 CPU = "penryn"; in getIntelProcessorTypeAndSubtype()
411 CPU = "nehalem"; in getIntelProcessorTypeAndSubtype()
419 CPU = "westmere"; in getIntelProcessorTypeAndSubtype()
426 CPU = "sandybridge"; in getIntelProcessorTypeAndSubtype()
432 CPU = "ivybridge"; in getIntelProcessorTypeAndSubtype()
442 CPU = "haswell"; in getIntelProcessorTypeAndSubtype()
452 CPU = "broadwell"; in getIntelProcessorTypeAndSubtype()
464 CPU = "skylake"; in getIntelProcessorTypeAndSubtype()
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/src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFSubtarget.cpp46 BPFSubtarget &BPFSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
49 initSubtargetFeatures(CPU, FS); in initializeSubtargetDependencies()
50 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in initializeSubtargetDependencies()
67 void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { in initSubtargetFeatures() argument
68 if (CPU == "probe") in initSubtargetFeatures()
69 CPU = sys::detail::getHostCPUNameForBPF(); in initSubtargetFeatures()
70 if (CPU == "generic" || CPU == "v1") in initSubtargetFeatures()
72 if (CPU == "v2") { in initSubtargetFeatures()
76 if (CPU == "v3") { in initSubtargetFeatures()
82 if (CPU == "v4") { in initSubtargetFeatures()
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/src/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp714 StringRef CPU; in getIntelProcessorTypeAndSubtype() local
718 CPU = "i386"; in getIntelProcessorTypeAndSubtype()
721 CPU = "i486"; in getIntelProcessorTypeAndSubtype()
725 CPU = "pentium-mmx"; in getIntelProcessorTypeAndSubtype()
728 CPU = "pentium"; in getIntelProcessorTypeAndSubtype()
739 CPU = "core2"; in getIntelProcessorTypeAndSubtype()
748 CPU = "penryn"; in getIntelProcessorTypeAndSubtype()
757 CPU = "nehalem"; in getIntelProcessorTypeAndSubtype()
765 CPU = "westmere"; in getIntelProcessorTypeAndSubtype()
772 CPU = "sandybridge"; in getIntelProcessorTypeAndSubtype()
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H A DRISCVTargetParser.cpp46 static const CPUInfo *getCPUInfoByName(StringRef CPU) { in getCPUInfoByName() argument
48 if (C.Name == CPU) in getCPUInfoByName()
53 bool hasFastScalarUnalignedAccess(StringRef CPU) { in hasFastScalarUnalignedAccess() argument
54 const CPUInfo *Info = getCPUInfoByName(CPU); in hasFastScalarUnalignedAccess()
58 bool hasFastVectorUnalignedAccess(StringRef CPU) { in hasFastVectorUnalignedAccess() argument
59 const CPUInfo *Info = getCPUInfoByName(CPU); in hasFastVectorUnalignedAccess()
63 bool parseCPU(StringRef CPU, bool IsRV64) { in parseCPU() argument
64 const CPUInfo *Info = getCPUInfoByName(CPU); in parseCPU()
85 StringRef getMArchFromMcpu(StringRef CPU) { in getMArchFromMcpu() argument
86 const CPUInfo *Info = getCPUInfoByName(CPU); in getMArchFromMcpu()
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/src/crypto/krb5/src/config/
H A Dwin-pre.in19 # Figure out the CPU
21 !if !defined(CPU) || "$(CPU)" == ""
22 CPU=$(PROCESSOR_ARCHITECTURE)
23 !endif # CPU
25 !if "$(CPU)" == ""
26 CPU=i386
30 !if ( "$(CPU)" == "X86" ) || ( "$(CPU)" == "x86" )
31 CPU=i386
32 !endif # CPU == X86
34 …f ( "$(CPU)" != "i386" ) && ( "$(CPU)" != "ALPHA" ) && ( "$(CPU)" != "ALPHA64" ) && ( "$(CPU)" != …
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/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRSubtarget.cpp30 AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU, in AVRSubtarget() argument
32 : AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(*this), in AVRSubtarget()
33 TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)) { in AVRSubtarget()
35 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in AVRSubtarget()
39 AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, in initializeSubtargetDependencies() argument
42 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in initializeSubtargetDependencies()
/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySubtarget.cpp28 WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
33 if (CPU.empty()) in initializeSubtargetDependencies()
34 CPU = "generic"; in initializeSubtargetDependencies()
36 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in initializeSubtargetDependencies()
41 const std::string &CPU, in WebAssemblySubtarget() argument
44 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), in WebAssemblySubtarget()
45 TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), in WebAssemblySubtarget()
/src/contrib/llvm-project/clang/lib/Basic/Targets/
H A DHexagon.cpp30 if (CPU == "hexagonv5") { in getTargetDefines()
37 } else if (CPU == "hexagonv55") { in getTargetDefines()
42 } else if (CPU == "hexagonv60") { in getTargetDefines()
48 } else if (CPU == "hexagonv62") { in getTargetDefines()
52 } else if (CPU == "hexagonv65") { in getTargetDefines()
56 } else if (CPU == "hexagonv66") { in getTargetDefines()
60 } else if (CPU == "hexagonv67") { in getTargetDefines()
63 } else if (CPU == "hexagonv67t") { in getTargetDefines()
66 } else if (CPU == "hexagonv68") { in getTargetDefines()
69 } else if (CPU == "hexagonv69") { in getTargetDefines()
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H A DMips.cpp32 return llvm::StringSwitch<bool>(CPU) in processorSupportsGPR64()
193 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); in getTargetDefines()
194 if (CPU == "octeon+") in getTargetDefines()
197 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); in getTargetDefines()
199 if (StringRef(CPU).starts_with("octeon")) in getTargetDefines()
202 if (CPU != "mips1") { in getTargetDefines()
242 Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU; in validateTarget()
248 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; in validateTarget()
261 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU; in validateTarget()
265 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" || in validateTarget()
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H A DMips.h43 std::string CPU; variable
78 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; in MipsTargetInfo()
85 return CPU == "mips32r6" || CPU == "mips64r6"; in isIEEE754_2008Default()
89 if (CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64") in getDefaultFPMode()
91 else if (CPU == "mips1") in getDefaultFPMode()
175 CPU = Name; in setCPU()
179 const std::string &getCPU() const { return CPU; } in getCPU()
182 StringRef CPU, in initFeatureMap() argument
184 if (CPU.empty()) in initFeatureMap()
185 CPU = getCPU(); in initFeatureMap()
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/src/contrib/llvm-project/llvm/lib/MC/
H A DMCSubtargetInfo.cpp112 for (auto &CPU : CPUTable) in Help() local
113 errs() << format(" %-*s - Select the %s processor.\n", MaxCPULen, CPU.Key, in Help()
114 CPU.Key); in Help()
140 for (auto &CPU : CPUTable) in cpuHelp() local
141 errs() << "\t" << CPU.Key << "\n"; in cpuHelp()
151 static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS, in getFeatures() argument
165 if (CPU == "help") in getFeatures()
169 else if (!CPU.empty()) { in getFeatures()
170 const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc); in getFeatures()
177 errs() << "'" << CPU << "' is not a recognized processor for this target" in getFeatures()
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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchSubtarget.cpp28 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, in initializeSubtargetDependencies() argument
31 if (CPU.empty() || CPU == "generic") in initializeSubtargetDependencies()
32 CPU = Is64Bit ? "generic-la64" : "generic-la32"; in initializeSubtargetDependencies()
35 TuneCPU = CPU; in initializeSubtargetDependencies()
37 ParseSubtargetFeatures(CPU, TuneCPU, FS); in initializeSubtargetDependencies()
84 LoongArchSubtarget::LoongArchSubtarget(const Triple &TT, StringRef CPU, in LoongArchSubtarget() argument
88 : LoongArchGenSubtargetInfo(TT, CPU, TuneCPU, FS), in LoongArchSubtarget()
90 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), in LoongArchSubtarget()
/src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp49 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { in selectMipsCPU() argument
50 if (CPU.empty() || CPU == "generic") { in selectMipsCPU()
53 CPU = "mips32r6"; in selectMipsCPU()
55 CPU = "mips64r6"; in selectMipsCPU()
58 CPU = "mips32"; in selectMipsCPU()
60 CPU = "mips64"; in selectMipsCPU()
63 return CPU; in selectMipsCPU()
79 StringRef CPU, StringRef FS) { in createMipsMCSubtargetInfo() argument
80 CPU = MIPS_MC::selectMipsCPU(TT, CPU); in createMipsMCSubtargetInfo()
81 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); in createMipsMCSubtargetInfo()
/src/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_fdr_controller.h147 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in recordPreamble() argument
148 if (UNLIKELY(LatestCPU != CPU || LatestTSC == 0)) { in recordPreamble()
152 LatestCPU = CPU; in recordPreamble()
157 W.writeMetadata<MetadataRecord::RecordKinds::NewCPUId>(CPU, TSC); in recordPreamble()
161 DCHECK_EQ(LatestCPU, CPU); in recordPreamble()
182 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in rewindRecords() argument
245 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in functionEnter() argument
250 auto PreambleStatus = recordPreamble(TSC, CPU); in functionEnter()
269 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in functionTailExit() argument
276 auto PreambleStatus = recordPreamble(TSC, CPU); in functionTailExit()
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/src/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DM68k.cpp34 std::string CPU = std::string(llvm::sys::getHostCPUName()); in getM68kTargetCPU() local
35 if (!CPU.empty() && CPU != "generic") in getM68kTargetCPU()
36 return CPU; in getM68kTargetCPU()
79 std::string CPU = m68k::getM68kTargetCPU(Args); in addFloatABIFeatures() local
81 if ((A && (CPU == "M68000" || CPU == "M68010")) || in addFloatABIFeatures()
83 CPU == "M68020") in addFloatABIFeatures()
85 else if (CPU == "M68030" || CPU == "M68040" || CPU == "M68060") in addFloatABIFeatures()
H A DRISCV.cpp86 StringRef CPU = A->getValue(); in getRISCVTargetFeatures() local
87 if (CPU == "native") in getRISCVTargetFeatures()
88 CPU = llvm::sys::getHostCPUName(); in getRISCVTargetFeatures()
90 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features); in getRISCVTargetFeatures()
92 if (llvm::RISCV::hasFastScalarUnalignedAccess(CPU)) in getRISCVTargetFeatures()
94 if (llvm::RISCV::hasFastVectorUnalignedAccess(CPU)) in getRISCVTargetFeatures()
313 StringRef CPU = A->getValue(); in getRISCVArch() local
314 if (CPU == "native") { in getRISCVArch()
315 CPU = llvm::sys::getHostCPUName(); in getRISCVArch()
317 if (CPU.starts_with("generic")) { in getRISCVArch()
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/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kSubtarget.cpp42 static StringRef selectM68kCPU(Triple TT, StringRef CPU) { in selectM68kCPU() argument
43 if (CPU.empty() || CPU == "generic") { in selectM68kCPU()
44 CPU = "M68000"; in selectM68kCPU()
46 return CPU; in selectM68kCPU()
51 M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS, in M68kSubtarget() argument
53 : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(), in M68kSubtarget()
54 InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)), in M68kSubtarget()
88 StringRef CPU, Triple TT, StringRef FS, const M68kTargetMachine &TM) { in initializeSubtargetDependencies() argument
89 std::string CPUName = selectM68kCPU(TT, CPU).str(); in initializeSubtargetDependencies()
/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVESubtarget.cpp28 VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
34 std::string CPUName = std::string(CPU); in initializeSubtargetDependencies()
39 ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPU, FS); in initializeSubtargetDependencies()
44 VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU, in VESubtarget() argument
46 : VEGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT), in VESubtarget()
47 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), in VESubtarget()
/src/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp32 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
35 TargetName = std::string(CPU.empty() ? "sm_30" : CPU); in initializeSubtargetDependencies()
52 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, in NVPTXSubtarget() argument
55 : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0), in NVPTXSubtarget()
57 TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {} in NVPTXSubtarget()
/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaTargetMachine.cpp31 static std::string computeDataLayout(const Triple &TT, StringRef CPU, in computeDataLayout() argument
46 StringRef CPU, StringRef FS, in XtensaTargetMachine() argument
52 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, in XtensaTargetMachine()
53 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), in XtensaTargetMachine()
60 StringRef CPU, StringRef FS, in XtensaTargetMachine() argument
65 : XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} in XtensaTargetMachine()
72 auto CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; in getSubtargetImpl() local
75 auto &I = SubtargetMap[CPU + FS]; in getSubtargetImpl()
81 I = std::make_unique<XtensaSubtarget>(TargetTriple, CPU, FS, *this); in getSubtargetImpl()
H A DXtensaSubtarget.cpp26 XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { in initializeSubtargetDependencies() argument
27 StringRef CPUName = CPU; in initializeSubtargetDependencies()
40 XtensaSubtarget::XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS, in XtensaSubtarget() argument
42 : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT), in XtensaSubtarget()
43 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), in XtensaSubtarget()
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.cpp32 StringRef CPU, StringRef TuneCPU, StringRef FS) { in initializeSubtargetDependencies() argument
33 if (CPU.empty()) in initializeSubtargetDependencies()
34 CPU = "generic"; in initializeSubtargetDependencies()
36 TuneCPU = CPU; in initializeSubtargetDependencies()
38 ParseSubtargetFeatures(CPU, TuneCPU, FS); in initializeSubtargetDependencies()
66 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, in SystemZSubtarget() argument
70 : SystemZGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT), in SystemZSubtarget()
72 InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)), in SystemZSubtarget()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp73 static std::string computeDataLayout(const Triple &TT, StringRef CPU, in computeDataLayout() argument
77 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); in computeDataLayout()
122 StringRef CPU, StringRef FS, in MipsTargetMachine() argument
128 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, in MipsTargetMachine()
129 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), in MipsTargetMachine()
132 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), in MipsTargetMachine()
134 DefaultSubtarget(TT, CPU, FS, isLittle, *this, std::nullopt), in MipsTargetMachine()
135 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", in MipsTargetMachine()
137 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", in MipsTargetMachine()
151 StringRef CPU, StringRef FS, in MipsebTargetMachine() argument
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/src/sys/contrib/device-tree/src/arm64/marvell/
H A Dac5x-rd-carrier-cn9131.dts6 * Utilizing the CN913x COM Express CPU module board.
8 * only maintains a PCIe link with the CPU module,
13 * which would allow it to use an external CN9131 CPU COM Express module,
19 * When the board boots in the external CPU mode, the internal CPU is disabled,
21 * is no need to describe this internal (disabled CPU) in the device tree.
23 * There is no CPU booting in this mode on the carrier, only on the
24 * CN9131 COM Express CPU module.
25 * What runs the Linux is the CN9131 on the COM Express CPU module,
34 model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";

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