11a82d4c0SDimitry Andric //===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
21a82d4c0SDimitry Andric //
3e6d15924SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4e6d15924SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5e6d15924SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
61a82d4c0SDimitry Andric //
71a82d4c0SDimitry Andric //===----------------------------------------------------------------------===//
81a82d4c0SDimitry Andric ///
91a82d4c0SDimitry Andric /// \file
10eb11fae6SDimitry Andric /// This file implements the WebAssembly-specific subclass of
111a82d4c0SDimitry Andric /// TargetSubtarget.
121a82d4c0SDimitry Andric ///
131a82d4c0SDimitry Andric //===----------------------------------------------------------------------===//
141a82d4c0SDimitry Andric
151a82d4c0SDimitry Andric #include "WebAssemblySubtarget.h"
1601095a5dSDimitry Andric #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
1701095a5dSDimitry Andric #include "WebAssemblyInstrInfo.h"
18c0981da4SDimitry Andric #include "llvm/MC/TargetRegistry.h"
191a82d4c0SDimitry Andric using namespace llvm;
201a82d4c0SDimitry Andric
211a82d4c0SDimitry Andric #define DEBUG_TYPE "wasm-subtarget"
221a82d4c0SDimitry Andric
231a82d4c0SDimitry Andric #define GET_SUBTARGETINFO_CTOR
241a82d4c0SDimitry Andric #define GET_SUBTARGETINFO_TARGET_DESC
251a82d4c0SDimitry Andric #include "WebAssemblyGenSubtargetInfo.inc"
261a82d4c0SDimitry Andric
271a82d4c0SDimitry Andric WebAssemblySubtarget &
initializeSubtargetDependencies(StringRef CPU,StringRef FS)28cfca06d7SDimitry Andric WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
29cfca06d7SDimitry Andric StringRef FS) {
301a82d4c0SDimitry Andric // Determine default and user-specified characteristics
31cfca06d7SDimitry Andric LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
321a82d4c0SDimitry Andric
33cfca06d7SDimitry Andric if (CPU.empty())
34cfca06d7SDimitry Andric CPU = "generic";
351a82d4c0SDimitry Andric
36b60736ecSDimitry Andric ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
371a82d4c0SDimitry Andric return *this;
381a82d4c0SDimitry Andric }
391a82d4c0SDimitry Andric
WebAssemblySubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const TargetMachine & TM)401a82d4c0SDimitry Andric WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
411a82d4c0SDimitry Andric const std::string &CPU,
421a82d4c0SDimitry Andric const std::string &FS,
431a82d4c0SDimitry Andric const TargetMachine &TM)
44b60736ecSDimitry Andric : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
456f8fc217SDimitry Andric TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
46b60736ecSDimitry Andric TLInfo(TM, *this) {}
471a82d4c0SDimitry Andric
enableAtomicExpand() const48e6d15924SDimitry Andric bool WebAssemblySubtarget::enableAtomicExpand() const {
49e6d15924SDimitry Andric // If atomics are disabled, atomic ops are lowered instead of expanded
50e6d15924SDimitry Andric return hasAtomics();
51e6d15924SDimitry Andric }
52e6d15924SDimitry Andric
enableMachineScheduler() const5301095a5dSDimitry Andric bool WebAssemblySubtarget::enableMachineScheduler() const {
5401095a5dSDimitry Andric // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
5501095a5dSDimitry Andric // enableMachineSchedDefaultSched overridden, it appears to have an overall
5601095a5dSDimitry Andric // negative effect for the kinds of register optimizations we're doing.
5701095a5dSDimitry Andric return false;
5801095a5dSDimitry Andric }
5901095a5dSDimitry Andric
useAA() const60dd58ef01SDimitry Andric bool WebAssemblySubtarget::useAA() const { return true; }
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