| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 790 struct optc *tgn10 = in dcn201_timing_generator_create() local
793 if (!tgn10) in dcn201_timing_generator_create()
796 tgn10->base.inst = instance; in dcn201_timing_generator_create()
797 tgn10->base.ctx = ctx; in dcn201_timing_generator_create()
799 tgn10->tg_regs = &tg_regs[instance]; in dcn201_timing_generator_create()
800 tgn10->tg_shift = &tg_shift; in dcn201_timing_generator_create()
801 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
803 dcn201_timing_generator_init(tgn10); in dcn201_timing_generator_create()
805 return &tgn10->base; in dcn201_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 609 struct optc *tgn10 = kzalloc_obj(struct optc); in dcn303_timing_generator_create() local
611 if (!tgn10) in dcn303_timing_generator_create()
614 tgn10->base.inst = instance; in dcn303_timing_generator_create()
615 tgn10->base.ctx = ctx; in dcn303_timing_generator_create()
617 tgn10->tg_regs = &optc_regs[instance]; in dcn303_timing_generator_create()
618 tgn10->tg_shift = &optc_shift; in dcn303_timing_generator_create()
619 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
621 dcn30_timing_generator_init(tgn10); in dcn303_timing_generator_create()
623 return &tgn10->base; in dcn303_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 637 struct optc *tgn10 = kzalloc_obj(struct optc); in dcn302_timing_generator_create() local
639 if (!tgn10) in dcn302_timing_generator_create()
642 tgn10->base.inst = instance; in dcn302_timing_generator_create()
643 tgn10->base.ctx = ctx; in dcn302_timing_generator_create()
645 tgn10->tg_regs = &optc_regs[instance]; in dcn302_timing_generator_create()
646 tgn10->tg_shift = &optc_shift; in dcn302_timing_generator_create()
647 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
649 dcn30_timing_generator_init(tgn10); in dcn302_timing_generator_create()
651 return &tgn10->base; in dcn302_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 1071 struct optc *tgn10 = in dcn21_timing_generator_create() local
1074 if (!tgn10) in dcn21_timing_generator_create()
1077 tgn10->base.inst = instance; in dcn21_timing_generator_create()
1078 tgn10->base.ctx = ctx; in dcn21_timing_generator_create()
1080 tgn10->tg_regs = &tg_regs[instance]; in dcn21_timing_generator_create()
1081 tgn10->tg_shift = &tg_shift; in dcn21_timing_generator_create()
1082 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
1084 dcn20_timing_generator_init(tgn10); in dcn21_timing_generator_create()
1086 return &tgn10->base; in dcn21_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 734 struct optc *tgn10 = in dcn10_timing_generator_create() local
737 if (!tgn10) in dcn10_timing_generator_create()
740 tgn10->base.inst = instance; in dcn10_timing_generator_create()
741 tgn10->base.ctx = ctx; in dcn10_timing_generator_create()
743 tgn10->tg_regs = &tg_regs[instance]; in dcn10_timing_generator_create()
744 tgn10->tg_shift = &tg_shift; in dcn10_timing_generator_create()
745 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
747 dcn10_timing_generator_init(tgn10); in dcn10_timing_generator_create()
749 return &tgn10->base; in dcn10_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 877 struct optc *tgn10 = in dcn301_timing_generator_create() local
880 if (!tgn10) in dcn301_timing_generator_create()
883 tgn10->base.inst = instance; in dcn301_timing_generator_create()
884 tgn10->base.ctx = ctx; in dcn301_timing_generator_create()
886 tgn10->tg_regs = &optc_regs[instance]; in dcn301_timing_generator_create()
887 tgn10->tg_shift = &optc_shift; in dcn301_timing_generator_create()
888 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
890 dcn301_timing_generator_init(tgn10); in dcn301_timing_generator_create()
892 return &tgn10->base; in dcn301_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1145 struct optc *tgn10 = in dcn31_timing_generator_create() local
1148 if (!tgn10) in dcn31_timing_generator_create()
1151 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1152 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1154 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1155 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1156 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1158 dcn314_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1160 return &tgn10->base; in dcn31_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1079 struct optc *tgn10 = in dcn31_timing_generator_create() local
1082 if (!tgn10) in dcn31_timing_generator_create()
1085 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1086 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1088 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1089 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1090 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1092 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1094 return &tgn10->base; in dcn31_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1044 struct optc *tgn10 = in dcn35_timing_generator_create() local
1047 if (!tgn10) in dcn35_timing_generator_create()
1057 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1058 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1060 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1061 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1062 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1064 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1066 return &tgn10->base; in dcn35_timing_generator_create()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1087 struct optc *tgn10 = in dcn31_timing_generator_create() local
1090 if (!tgn10) in dcn31_timing_generator_create()
1093 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1094 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1096 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1097 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1098 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1100 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1102 return &tgn10->base; in dcn31_timing_generator_create()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1024 struct optc *tgn10 = in dcn321_timing_generator_create() local
1027 if (!tgn10) in dcn321_timing_generator_create()
1037 tgn10->base.inst = instance; in dcn321_timing_generator_create()
1038 tgn10->base.ctx = ctx; in dcn321_timing_generator_create()
1040 tgn10->tg_regs = &optc_regs[instance]; in dcn321_timing_generator_create()
1041 tgn10->tg_shift = &optc_shift; in dcn321_timing_generator_create()
1042 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()
1044 dcn32_timing_generator_init(tgn10); in dcn321_timing_generator_create()
1046 return &tgn10->base; in dcn321_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1051 struct optc *tgn10 = in dcn35_timing_generator_create() local
1054 if (!tgn10) in dcn35_timing_generator_create()
1064 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1065 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1067 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1068 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1069 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1071 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1073 return &tgn10->base; in dcn35_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1064 struct optc *tgn10 = in dcn35_timing_generator_create() local
1067 if (!tgn10) in dcn35_timing_generator_create()
1077 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1078 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1080 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1081 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1082 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1084 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1086 return &tgn10->base; in dcn35_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1086 struct optc *tgn10 = in dcn31_timing_generator_create() local
1089 if (!tgn10) in dcn31_timing_generator_create()
1092 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1093 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1095 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1096 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1097 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1099 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1101 return &tgn10->base; in dcn31_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1026 struct optc *tgn10 = in dcn401_timing_generator_create() local
1029 if (!tgn10) in dcn401_timing_generator_create()
1038 tgn10->base.inst = instance; in dcn401_timing_generator_create()
1039 tgn10->base.ctx = ctx; in dcn401_timing_generator_create()
1041 tgn10->tg_regs = &optc_regs[instance]; in dcn401_timing_generator_create()
1042 tgn10->tg_shift = &optc_shift; in dcn401_timing_generator_create()
1043 tgn10->tg_mask = &optc_mask; in dcn401_timing_generator_create()
1045 dcn401_timing_generator_init(tgn10); in dcn401_timing_generator_create()
1047 return &tgn10->base; in dcn401_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 921 struct optc *tgn10 = in dcn30_timing_generator_create() local
924 if (!tgn10) in dcn30_timing_generator_create()
927 tgn10->base.inst = instance; in dcn30_timing_generator_create()
928 tgn10->base.ctx = ctx; in dcn30_timing_generator_create()
930 tgn10->tg_regs = &optc_regs[instance]; in dcn30_timing_generator_create()
931 tgn10->tg_shift = &optc_shift; in dcn30_timing_generator_create()
932 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
934 dcn30_timing_generator_init(tgn10); in dcn30_timing_generator_create()
936 return &tgn10->base; in dcn30_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 913 struct optc *tgn10 = in dcn20_timing_generator_create() local
916 if (!tgn10) in dcn20_timing_generator_create()
919 tgn10->base.inst = instance; in dcn20_timing_generator_create()
920 tgn10->base.ctx = ctx; in dcn20_timing_generator_create()
922 tgn10->tg_regs = &tg_regs[instance]; in dcn20_timing_generator_create()
923 tgn10->tg_shift = &tg_shift; in dcn20_timing_generator_create()
924 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
926 dcn20_timing_generator_init(tgn10); in dcn20_timing_generator_create()
928 return &tgn10->base; in dcn20_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1030 struct optc *tgn10 = in dcn32_timing_generator_create() local
1033 if (!tgn10) in dcn32_timing_generator_create()
1043 tgn10->base.inst = instance; in dcn32_timing_generator_create()
1044 tgn10->base.ctx = ctx; in dcn32_timing_generator_create()
1046 tgn10->tg_regs = &optc_regs[instance]; in dcn32_timing_generator_create()
1047 tgn10->tg_shift = &optc_shift; in dcn32_timing_generator_create()
1048 tgn10->tg_mask = &optc_mask; in dcn32_timing_generator_create()
1050 dcn32_timing_generator_init(tgn10); in dcn32_timing_generator_create()
1052 return &tgn10->base; in dcn32_timing_generator_create()
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