| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 703 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
738 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
982 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1017 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
1030 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1035 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1042 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1066 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1187 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1195 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 742 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
777 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1038 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1073 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1086 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1091 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1098 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1122 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1246 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1254 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1084 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1120 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1133 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1138 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1145 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1168 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1184 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1213 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1237 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1335 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1140 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1410 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1444 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1462 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1469 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1492 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1508 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1566 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1206 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1473 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1506 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1519 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1524 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1531 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1554 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1570 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1607 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1631 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1143 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1473 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_destruct()
1503 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn36_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_destruct()
1521 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1528 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1551 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn36_resource_destruct()
1567 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1625 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1663 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1156 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1486 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
1529 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
1534 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1541 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1564 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1580 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1638 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1676 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1147 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1449 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1462 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1467 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1474 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1497 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1513 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1550 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1574 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1136 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1466 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
1509 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
1514 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1521 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1544 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1560 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1618 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1656 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1148 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1414 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1448 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1461 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1466 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1473 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1512 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1549 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1573 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1113 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1149 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1162 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1167 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1174 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1197 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1253 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1277 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1476 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1506 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 379 static const struct resource_caps res_cap = { variable
849 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
924 pool->base.res_cap = &res_cap; in dce60_construct()
932 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
933 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1048 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1122 pool->base.res_cap = &res_cap_61; in dce61_construct()
1246 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1320 pool->base.res_cap = &res_cap_64; in dce64_construct()
1443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 379 static const struct resource_caps res_cap = { variable
855 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
930 pool->base.res_cap = &res_cap; in dce80_construct()
938 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
939 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1059 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1133 pool->base.res_cap = &res_cap_81; in dce81_construct()
1259 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1333 pool->base.res_cap = &res_cap_83; in dce83_construct()
1457 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1403 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1432 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1523 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1551 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1706 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
168 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
262 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
539 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
695 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1428 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_destruct()
1458 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn401_resource_destruct()
1471 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn401_resource_destruct()
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1483 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1506 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn401_resource_destruct()
1522 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1549 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1579 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
1890 pool->base.res_cap = &res_cap_dcn4_01; in dcn401_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1122 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1158 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1171 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1176 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1183 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1373 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1387 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1401 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2275 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2297 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 379 static const struct resource_caps res_cap = { variable
806 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
1040 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1115 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1116 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1173 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1422 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1452 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1470 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1477 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1500 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1543 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1571 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1661 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 499 static const struct resource_caps res_cap = { variable
629 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1078 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1082 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1083 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1229 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 983 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
988 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1130 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1229 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1264 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1273 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1289 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 687 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
722 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
735 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
740 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
747 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1423 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1433 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1647 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1691 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 517 static const struct resource_caps res_cap = { variable
978 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1362 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1364 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1378 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1646 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 806 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1237 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1244 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1245 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1380 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
300 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
333 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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