| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1174 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1240 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1177 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1190 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1181 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1170 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1182 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1111 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1107 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1130 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
| H A D | dpcs_3_1_4_offset.h | 6257 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dpcs_4_2_2_offset.h | 594 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dpcs_4_2_0_offset.h | 597 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dpcs_4_2_3_offset.h | 630 #define regDC_PINSTRAPS_BASE_IDX … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
| H A D | dcn_3_2_1_offset.h | 10959 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_6_0_offset.h | 11879 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_5_0_offset.h | 9798 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_1_4_offset.h | 10909 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_5_1_offset.h | 9777 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_1_2_offset.h | 11806 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_2_0_offset.h | 10950 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_1_5_offset.h | 11551 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_4_1_0_offset.h | 11236 #define regDC_PINSTRAPS_BASE_IDX … macro
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| H A D | dcn_3_1_6_offset.h | 12042 #define regDC_PINSTRAPS_BASE_IDX … macro
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