Home
last modified time | relevance | path

Searched refs:phydev_err (Results 1 – 25 of 29) sorted by relevance

12

/linux/drivers/net/phy/aquantia/
H A Daquantia_firmware.c141 phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n", in aqr_fw_load_memory()
164 phydev_err(phydev, "bad firmware CRC in firmware\n"); in aqr_fw_boot()
169 phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n", in aqr_fw_boot()
177 phydev_err(phydev, "bad primary offset in firmware\n"); in aqr_fw_boot()
187 phydev_err(phydev, "bad fw_header in firmware\n"); in aqr_fw_boot()
196 phydev_err(phydev, "bad iram offset in firmware\n"); in aqr_fw_boot()
203 phydev_err(phydev, "invalid iram size in firmware\n"); in aqr_fw_boot()
210 phydev_err(phydev, "bad dram offset in firmware\n"); in aqr_fw_boot()
217 phydev_err(phydev, "invalid dram size in firmware\n"); in aqr_fw_boot()
226 phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n"); in aqr_fw_boot()
[all …]
H A Daquantia_main.c167 phydev_err(phydev, "Reading HW Statistics failed for %s\n", in aqr107_get_stats()
700 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", in aqr_wait_reset_complete()
1032 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); in aqr_gen1_wait_processor_intensive_op()
/linux/drivers/net/phy/
H A Dair_en8811h.c301 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_write()
351 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_read()
427 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_modify()
481 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_write_buf()
503 phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); in en8811h_wait_mcu_ready()
543 phydev_err(phydev, "CRC Check is not ready (%u)\n", pbus_value); in an8811hb_check_crc()
656 phydev_err(phydev, "Load firmware failed: %d\n", ret); in en8811h_load_firmware()
923 phydev_err(phydev, "LED mode %d is not supported\n", mode); in air_leds_init()
930 phydev_err(phydev, "LED%d init failed: %d\n", i, ret); in air_leds_init()
1162 phydev_err(phydev, "Failed to disable leds: %d\n", ret); in en8811h_leds_setup()
[all …]
H A Dnxp-c45-tja11xx.c320 phydev_err(phydev, "Trying to read a reg field of size 0.\n"); in nxp_c45_read_reg_field()
345 phydev_err(phydev, "Trying to write a reg field of size 0.\n"); in nxp_c45_write_reg_field()
362 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_set_reg_field()
373 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_clear_reg_field()
1413 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay()
1418 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
1507 phydev_err(phydev, in nxp_c45_get_delays()
1523 phydev_err(phydev, in nxp_c45_get_delays()
1544 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
1555 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
[all …]
H A Ddp83869.c364 phydev_err(phydev, "Failed to read RX CFG\n"); in dp83869_get_wol()
381 phydev_err(phydev, "Failed to read RX SOP 1\n"); in dp83869_get_wol()
391 phydev_err(phydev, "Failed to read RX SOP 2\n"); in dp83869_get_wol()
401 phydev_err(phydev, "Failed to read RX SOP 3\n"); in dp83869_get_wol()
473 phydev_err(phydev, in dp83869_set_downshift()
713 phydev_err(phydev, "selected op-mode is not valid with MII mode\n"); in dp83869_configure_mode()
H A Ddp83867.c455 phydev_err(phydev, in dp83867_set_downshift()
541 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n"); in dp83867_of_init_io_impedance()
570 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
590 phydev_err(phydev, in dp83867_of_init()
600 phydev_err(phydev, in dp83867_of_init()
623 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
634 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
H A Das21xxx.c322 phydev_err(phydev, "wrong origin mdio_indirect_status: %x\n", val); in aeon_firmware_boot()
366 phydev_err(phydev, "failed to find FW file %s (%d)\n", in aeon_firmware_load()
482 phydev_err(phydev, "failed to send ipc msg for %x: %d\n", in aeon_ipc_send_msg()
562 phydev_err(phydev, "Invalid IPC status on sync parity: %x\n", in aeon_ipc_sync_parity()
685 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in as21xxx_read_c22_lpa()
687 phydev_err(phydev, "Master/Slave resolution failed\n"); in as21xxx_read_c22_lpa()
H A Ddp83822.c654 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", in dp8382x_config_rmii_mode()
788 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n"); in dp83822_of_init_leds()
794 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n"); in dp83822_of_init_leds()
800 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n"); in dp83822_of_init_leds()
829 phydev_err(phydev, in dp83822_of_init()
850 phydev_err(phydev, in dp83822_of_init()
867 phydev_err(phydev, in dp83822_of_init()
H A Dcortina.c68 phydev_err(phydev, "Error matching phy with %s driver\n", in cortina_probe()
H A Drockchip.c116 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
H A Dphy_device.c740 phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n", in phy_request_driver_module()
1123 phydev_err(phydev, "failed to initialize\n"); in phy_device_register()
1129 phydev_err(phydev, "failed to add\n"); in phy_device_register()
1757 phydev_err(phydev, "failed to get the bus module\n"); in phy_attach_direct()
1776 phydev_err(phydev, "failed to get the device driver module\n"); in phy_attach_direct()
1825 phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); in phy_attach_direct()
2522 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in genphy_read_lpa()
2524 phydev_err(phydev, "Master/Slave resolution failed\n"); in genphy_read_lpa()
3146 phydev_err(phydev, "Delay %d is out of range\n", delay); in phy_get_internal_delay()
3168 phydev_err(phydev, "error finding internal delay index for %d\n", in phy_get_internal_delay()
H A Dmicrel.c668 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led()
687 phydev_err(phydev, "failed to disable broadcast address\n"); in kszphy_broadcast_disable()
707 phydev_err(phydev, "failed to disable NAND tree mode\n"); in kszphy_nand_tree_disable()
721 phydev_err(phydev, in kszphy_config_reset()
1326 phydev_err(phydev, "failed to force the phy to master mode\n"); in ksz9031_config_init()
2513 phydev_err(phydev, "invalid led mode: 0x%02x\n", in kszphy_parse_led_mode()
2667 phydev_err(phydev, "Failed to enable rmii-ref clock\n"); in kszphy_probe()
2684 phydev_err(phydev, "Clock rate out of range: %ld\n", in kszphy_probe()
3054 phydev_err(phydev, "Error: phy_write has returned error %d\n", in lanphy_write_page_reg()
3075 phydev_err(phydev, "__phy_modify_changed() failed: %pe\n", in lanphy_modify_page_reg()
[all …]
H A Dmotorcomm.c1239 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in ytphy_utp_read_lpa()
1241 phydev_err(phydev, "Master/Slave resolution failed\n"); in ytphy_utp_read_lpa()
2515 phydev_err(phydev, "Failed to select page: %d\n", in yt8821_serdes_init()
2550 phydev_err(phydev, "Failed to select page: %d\n", in yt8821_utp_init()
2741 phydev_err(phydev, "Failed to select page: %d\n", in yt8821_auto_sleep_config()
H A Dmxl-gpy.c408 phydev_err(phydev, "Error: MDIO register access failed: %d\n", in gpy_2500basex_chk()
430 phydev_err(phydev, "Error: MMD register access failed: %d\n", in gpy_sgmii_aneg_en()
596 phydev_err(phydev, in gpy_update_interface()
H A Dmicrochip.c359 phydev_err(phydev, "Link change process failed %pe\n", ERR_PTR(ret)); in lan88xx_link_change_notify()
H A Dadin.c517 phydev_err(phydev, "invalid adi,phy-output-clock\n"); in adin_config_clk_out()
641 phydev_err(phydev, in adin_cl45_to_adin_reg()
H A Dmicrochip_t1s.c321 phydev_err(phydev, "PHY reset failed\n"); in lan867x_check_reset_complete()
H A Dphy.c540 phydev_err(phydev, "Error while aborting cable test"); in phy_abort_cable_test()
1342 phydev_err(phydev, "PHY-device data unsafe context\n"); in phy_process_error()
/linux/drivers/net/phy/qcom/
H A Dat803x.c302 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); in at803x_parse_dt()
310 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); in at803x_parse_dt()
332 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); in at803x_parse_dt()
354 phydev_err(phydev, "invalid qca,clk-out-strength\n"); in at803x_parse_dt()
759 phydev_err(phydev, "failed to register VDDIO regulator\n"); in at8031_register_regulators()
765 phydev_err(phydev, "failed to register VDDH regulator\n"); in at8031_register_regulators()
826 phydev_err(phydev, "failed to get VDDIO regulator\n"); in at8031_parse_dt()
H A Dqca808x.c617 phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); in qca808x_led_polarity_set()
/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c403 phydev_err(phydev, "Calibration cycle timeout\n"); in cal_cycle()
1148 phydev_err(phydev, "cal %d failed\n", cal_item); in start_cal()
1175 phydev_err(phydev, "invalid efuse data\n"); in mt798x_phy_calibration()
/linux/include/linux/
H A Dphy.h1718 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1818 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
2222 #define phydev_err(_phydev, format, args...) \ macro
/linux/net/ethtool/
H A Dcabletest.c52 phydev_err(phydev, "%s: Error %pe\n", __func__, ERR_PTR(err)); in ethnl_cable_test_started()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c624 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", in rtl8211f_config_rgmii_delay()
641 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", in rtl8211f_config_rgmii_delay()
/linux/drivers/net/phy/mscc/
H A Dmscc_main.c285 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
444 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()

12