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Searched refs:phy_write_mmd (Results 1 – 25 of 43) sorted by relevance

12

/linux/drivers/net/phy/qcom/
H A Dqca808x.c108 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
110 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, in qca808x_phy_fast_retrain_config()
112 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, in qca808x_phy_fast_retrain_config()
114 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, in qca808x_phy_fast_retrain_config()
116 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, in qca808x_phy_fast_retrain_config()
118 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
120 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, in qca808x_phy_fast_retrain_config()
122 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, in qca808x_phy_fast_retrain_config()
124 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, in qca808x_phy_fast_retrain_config()
126 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, in qca808x_phy_fast_retrain_config()
[all …]
H A Dat803x.c1000 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, in ipq5018_cable_test_start()
1002 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4, in ipq5018_cable_test_start()
1004 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5, in ipq5018_cable_test_start()
1006 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6, in ipq5018_cable_test_start()
1008 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7, in ipq5018_cable_test_start()
1010 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9, in ipq5018_cable_test_start()
1012 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13, in ipq5018_cable_test_start()
1014 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, in ipq5018_cable_test_start()
1038 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER, in ipq5018_config_init()
1040 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER, in ipq5018_config_init()
[all …]
H A Dqca83xx.c110 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init()
113 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init()
/linux/drivers/net/phy/
H A Dnxp-c45-tja11xx.c424 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
426 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
430 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
464 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
472 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
527 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
566 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
605 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
648 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
[all …]
H A Dmarvell-88q2xxx.c226 ret = phy_write_mmd(phydev, vals->devad, vals->regnum, in mv88q2xxx_write_mmd_vals()
242 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48); in mv88q2xxx_soft_reset()
247 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_CTRL, in mv88q2xxx_soft_reset()
259 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc); in mv88q2xxx_soft_reset()
265 return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58); in mv88q2xxx_soft_reset()
528 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
537 return phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
541 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
546 return phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
931 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q222x_cable_test_start()
[all …]
H A Dmicrochip_t1s.c151 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb_indirect_read()
156 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb_indirect_read()
212 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], in lan865x_write_cfg_params()
276 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
353 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
371 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
429 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revd0_link_active_selection()
480 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revd0_config_init()
H A Dintel-xway.c251 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_init_leds()
255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_init_leds()
268 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_init_leds()
269 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_init_leds()
270 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_init_leds()
271 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_init_leds()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_init_leds()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_init_leds()
387 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), 0); in xway_gphy_led_brightness_set()
391 return phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), 0); in xway_gphy_led_brightness_set()
[all …]
H A Ddp83869.c286 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
292 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
298 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
310 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
316 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
321 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
346 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg); in dp83869_set_wol()
718 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, in dp83869_configure_mode()
753 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
765 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
[all …]
H A Ddp83tc811.c113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1, in dp83811_set_wol()
115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2, in dp83811_set_wol()
117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3, in dp83811_set_wol()
128 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
131 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
134 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
148 return phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
H A Ddp83tg720.c341 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
346 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
351 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4, in dp83tg720_cable_test_start()
356 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405, in dp83tg720_cable_test_start()
361 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F, in dp83tg720_cable_test_start()
576 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3, in dp83tg720_config_init()
H A Ddp83867.c224 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol()
226 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol()
228 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol()
237 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol()
239 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, in dp83867_set_wol()
241 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, in dp83867_set_wol()
263 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); in dp83867_set_wol()
783 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
785 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
791 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
[all …]
H A Dmicrel.c930 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); in ksz8061_config_init()
1142 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values()
1150 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, in ksz9031_center_flp_timing()
1155 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, in ksz9031_center_flp_timing()
1171 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, in ksz9031_enable_edpd()
1209 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, in ksz9031_config_rgmii_delay()
1215 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay()
1223 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay()
1231 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, in ksz9031_config_rgmii_delay()
1384 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
[all …]
H A Dsmsc.c327 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_phy_config_init()
333 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR, in lan874x_phy_config_init()
423 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
429 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
437 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask); in lan874x_set_wol_pattern()
447 phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0); in lan874x_set_wol_pattern()
533 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, in lan874x_set_wol()
540 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_set_wol()
H A Dbcm87xx.c69 ret = phy_write_mmd(phydev, devid, reg, val); in bcm87xx_of_reg_init()
155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
H A Dmicrochip_t1.c1331 ret = phy_write_mmd(phydev, reg_map[i].mmd, in lan887x_phy_config()
1453 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST, in lan887x_phy_reset()
1562 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, in lan887x_config_intr()
1565 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, in lan887x_config_intr()
1616 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST, in lan887x_cd_reset()
1675 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in lan887x_cable_test_prep()
1680 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038); in lan887x_cable_test_prep()
1691 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg, in lan887x_cable_test_prep()
1698 rc = phy_write_mmd(phydev, values[i].mmd, in lan887x_cable_test_prep()
1727 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_prep()
[all …]
H A Ddp83td510.c535 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
547 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
739 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2, in dp83td510_cable_test_start()
747 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1, in dp83td510_cable_test_start()
758 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E, in dp83td510_cable_test_start()
763 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3, in dp83td510_cable_test_start()
H A Dair_en8811h.c722 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_blink_set()
858 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), in air_led_hw_control_set()
895 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, in air_leds_init()
900 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, in air_leds_init()
1365 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, in en8811h_config_init()
1369 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, in en8811h_config_init()
1373 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_config_init()
1377 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_config_init()
1522 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_clear_intr()
1527 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_clear_intr()
H A Ddp83822.c229 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, in dp83822_config_wol()
231 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, in dp83822_config_wol()
233 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, in dp83822_config_wol()
244 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
247 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
250 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
264 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
1045 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | in dp83822_resume()
H A Das21xxx.c308 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR, in aeon_firmware_boot()
330 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
336 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
342 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CMD, cmd); in aeon_ipc_send_cmd()
472 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i), in aeon_ipc_send_msg()
H A Dmarvell-88x2222.c78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
/linux/drivers/net/phy/aquantia/
H A Daquantia_firmware.c96 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
99 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
102 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
116 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5, in aqr_fw_load_memory()
118 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6, in aqr_fw_load_memory()
121 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1, in aqr_fw_load_memory()
262 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
290 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
H A Daquantia_main.c265 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
270 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr()
275 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, in aqr_config_intr()
402 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); in aqr105_setup_forced()
405 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend); in aqr105_setup_forced()
408 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10); in aqr105_setup_forced()
/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c613 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); in tx_r50_fill_result()
858 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); in mt7981_phy_finetune()
894 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); in mt7981_phy_finetune()
897 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); in mt7981_phy_finetune()
898 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
899 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); in mt7981_phy_finetune()
900 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
901 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); in mt7981_phy_finetune()
902 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
903 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); in mt7981_phy_finetune()
[all …]
H A Dmtk-2p5ge.c88 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100); in mt798x_2p5ge_phy_load_fw()
89 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df); in mt798x_2p5ge_phy_load_fw()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c1369 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); in rtl822x_set_serdes_option_mode()
1381 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); in rtl822x_set_serdes_option_mode()
1385 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); in rtl822x_set_serdes_option_mode()
1389 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); in rtl822x_set_serdes_option_mode()
1406 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); in rtl822x_serdes_write()
1410 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); in rtl822x_serdes_write()
1414 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, in rtl822x_serdes_write()
1692 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in rtl8224_sram_read()
2074 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, in rtl8221b_config_intr()
2077 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, in rtl8221b_config_intr()

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