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Searched refs:io_base (Results 1 – 25 of 175) sorted by relevance

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/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
H A Dmeson_crtc.c100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
143 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
192 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
246 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
H A Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 priv->io_base + _REG(VPP_DUMMY_DATA)); in meson_vpp_init()
[all …]
H A Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
H A Dmeson_osd_afbcd.c85 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
133 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
163 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
H A Dflipper-pic.c49 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_mask_and_ack() local
52 clrbits32(io_base + FLIPPER_IMR, mask); in flipper_pic_mask_and_ack()
54 out_be32(io_base + FLIPPER_ICR, mask); in flipper_pic_mask_and_ack()
60 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_ack() local
63 out_be32(io_base + FLIPPER_ICR, 1 << irq); in flipper_pic_ack()
69 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_mask() local
71 clrbits32(io_base + FLIPPER_IMR, 1 << irq); in flipper_pic_mask()
77 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_unmask() local
79 setbits32(io_base + FLIPPER_IMR, 1 << irq); in flipper_pic_unmask()
116 static void __flipper_quiesce(void __iomem *io_base) in __flipper_quiesce() argument
[all …]
H A Dhlwd-pic.c45 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask_and_ack() local
48 clrbits32(io_base + HW_BROADWAY_IMR, mask); in hlwd_pic_mask_and_ack()
49 out_be32(io_base + HW_BROADWAY_ICR, mask); in hlwd_pic_mask_and_ack()
55 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_ack() local
57 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); in hlwd_pic_ack()
63 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask() local
65 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_mask()
71 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_unmask() local
73 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_unmask()
76 clrbits32(io_base + HW_STARLET_IMR, 1 << irq); in hlwd_pic_unmask()
[all …]
/linux/sound/isa/
H A Dsscape.c133 unsigned io_base; member
189 static inline void sscape_write_unsafe(unsigned io_base, enum GA_REG reg, in sscape_write_unsafe() argument
192 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_write_unsafe()
193 outb(val, ODIE_DATA_IO(io_base)); in sscape_write_unsafe()
204 sscape_write_unsafe(s->io_base, reg, val); in sscape_write()
211 static inline unsigned char sscape_read_unsafe(unsigned io_base, in sscape_read_unsafe() argument
214 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_read_unsafe()
215 return inb(ODIE_DATA_IO(io_base)); in sscape_read_unsafe()
221 static inline void set_host_mode_unsafe(unsigned io_base) in set_host_mode_unsafe() argument
223 outb(0x0, HOST_CTRL_IO(io_base)); in set_host_mode_unsafe()
[all …]
/linux/drivers/crypto/hisilicon/zip/
H A Ddae_main.c72 val = readl(qm->io_base + DAE_MEM_START_OFFSET); in hisi_dae_set_user_domain()
74 writel(val, qm->io_base + DAE_MEM_START_OFFSET); in hisi_dae_set_user_domain()
75 ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val, in hisi_dae_set_user_domain()
119 axi_val = readl(qm->io_base + DAE_AXI_CFG_OFFSET); in hisi_dae_master_ooo_ctrl()
128 writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET); in hisi_dae_master_ooo_ctrl()
129 writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET); in hisi_dae_master_ooo_ctrl()
138 writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_SOURCE_OFFSET); in hisi_dae_hw_error_enable()
141 writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET); in hisi_dae_hw_error_enable()
142 writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET); in hisi_dae_hw_error_enable()
143 writel(DAE_ERR_FE_MASK, qm->io_base + DAE_ERR_FE_OFFSET); in hisi_dae_hw_error_enable()
[all …]
H A Dzip_main.c475 val = readl_relaxed(qm->io_base + HZIP_LIT_LEN_EN_OFFSET); in hisi_zip_literal_set()
479 writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET); in hisi_zip_literal_set()
486 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
493 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
506 val = readl(qm->io_base + offset); in hisi_zip_wait_sva_ready()
531 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
533 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
535 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, in hisi_zip_close_sva_prefetch()
553 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
555 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
[all …]
/linux/drivers/watchdog/
H A Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); in ni903x_wdd_set_timeout()
71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); in ni903x_wdd_set_timeout()
72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); in ni903x_wdd_set_timeout()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
[all …]
H A Dnic7018_wdt.c47 u16 io_base; member
97 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
112 control = inb(wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
113 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
115 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
117 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
118 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); in nic7018_start()
127 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
128 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
129 outb(0xF0, wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_stop()
[all …]
/linux/drivers/crypto/hisilicon/sec2/
H A Dsec_main.c479 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
487 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
500 val = readl(qm->io_base + offset); in sec_wait_sva_ready()
525 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
527 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
529 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, in sec_close_sva_prefetch()
547 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
549 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
551 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, in sec_open_sva_prefetch()
570 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
[all …]
/linux/sound/soc/spear/
H A Dspdif_in.c38 void *io_base; member
52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_configure()
53 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_configure()
74 writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_shutdown()
79 u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
128 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
131 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_trigger()
137 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
[all …]
H A Dspdif_out.c39 void __iomem *io_base; member
46 writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
48 writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET, in spdif_out_configure()
49 host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
54 host->io_base + SPDIF_OUT_CFG); in spdif_out_configure()
56 writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR); in spdif_out_configure()
57 writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR); in spdif_out_configure()
99 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
102 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
165 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_trigger()
[all …]
/linux/drivers/crypto/intel/keembay/
H A Docs-hcu.c173 return readl_poll_timeout(hcu_dev->io_base + OCS_HCU_STATUS, val, in ocs_hcu_wait_busy()
182 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_done_irq_en()
186 hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_done_irq_en()
192 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_DMA_MSI_ISR); in ocs_hcu_dma_irq_en()
196 hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_dma_irq_en()
198 writel(HCU_DMA_MSI_UNMASK, hcu_dev->io_base + OCS_HCU_DMA_MSI_MASK); in ocs_hcu_dma_irq_en()
203 writel(HCU_IRQ_DISABLE, hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_irq_dis()
204 writel(HCU_DMA_MSI_DISABLE, hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_irq_dis()
270 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_intermediate_data()
272 data->msg_len_lo = readl(hcu_dev->io_base + OCS_HCU_MSG_LEN_LO); in ocs_hcu_get_intermediate_data()
[all …]
/linux/drivers/fpga/
H A Dts73xx-fpga.c31 void __iomem *io_base; member
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
59 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, in ts73xx_fpga_write()
65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
88 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
[all …]
/linux/drivers/crypto/hisilicon/hpre/
H A Dhpre_main.c485 val = readl(qm->io_base + HPRE_SVA_PREFTCH_DFX4); in hpre_wait_sva_ready()
509 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
510 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
518 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
519 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
565 qm->io_base + offset + HPRE_CORE_ENB); in hpre_set_cluster()
566 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); in hpre_set_cluster()
567 ret = readl_relaxed_poll_timeout(qm->io_base + offset + in hpre_set_cluster()
592 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
595 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
[all …]
/linux/drivers/hwspinlock/
H A Du8500_hsem.c90 void __iomem *io_base; in u8500_hsem_probe() local
97 io_base = devm_platform_ioremap_resource(pdev, 0); in u8500_hsem_probe()
98 if (IS_ERR(io_base)) in u8500_hsem_probe()
99 return PTR_ERR(io_base); in u8500_hsem_probe()
102 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
106 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
129 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
/linux/drivers/input/keyboard/
H A Dspear-keyboard.c56 void __iomem *io_base; member
74 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
84 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
95 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
119 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
120 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
123 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
125 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
136 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
138 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
[all …]
/linux/drivers/mtd/spi-nor/controllers/
H A Dnxp-spifi.c56 void __iomem *io_base; member
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
114 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); in nxp_spifi_set_memory_mode_on()
115 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_set_memory_mode_on()
140 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
143 *buf++ = readb(spifi->io_base + SPIFI_DATA); in nxp_spifi_read_reg()
164 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
167 writeb(*buf++, spifi->io_base + SPIFI_DATA); in nxp_spifi_write_reg()
[all …]
/linux/drivers/mtd/nand/raw/
H A Dlpc32xx_slc.c219 void __iomem *io_base; member
241 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); in lpc32xx_nand_setup()
245 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
246 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
248 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
264 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
277 tmp = readl(SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
282 writel(tmp, SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
286 writel(cmd, SLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, SLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
H A Dlpc32xx_mlc.c180 void __iomem *io_base; member
236 writel(MLCCMD_RESET, MLC_CMD(host->io_base)); in lpc32xx_nand_setup()
246 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
250 writel(tmp, MLC_ICR(host->io_base)); in lpc32xx_nand_setup()
254 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
265 writel(tmp, MLC_TIME_REG(host->io_base)); in lpc32xx_nand_setup()
269 MLC_IRQ_MR(host->io_base)); in lpc32xx_nand_setup()
272 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); in lpc32xx_nand_setup()
285 writel(cmd, MLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
287 writel(cmd, MLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
/linux/drivers/mtd/devices/
H A Dspear_smi.c174 void __iomem *io_base; member
229 ctrlreg1 = readl(dev->io_base + SMI_CR1); in spear_smi_read_sr()
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
248 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
301 status = readl(dev->io_base + SMI_SR); in spear_smi_int_handler()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
[all …]
/linux/drivers/mfd/
H A Dtqmx86.c212 void __iomem *io_base, u8 reg_shift) in tqmx86_setup_irq() argument
235 val = ioread8(io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_setup_irq()
239 iowrite8(val, io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_setup_irq()
240 readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_setup_irq()
254 void __iomem *io_base; in tqmx86_probe() local
257 io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE); in tqmx86_probe()
258 if (!io_base) in tqmx86_probe()
261 board_id = ioread8(io_base + TQMX86_REG_BOARD_ID); in tqmx86_probe()
262 sauc = ioread8(io_base + TQMX86_REG_SAUC); in tqmx86_probe()
264 rev = ioread8(io_base + TQMX86_REG_BOARD_REV); in tqmx86_probe()
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