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Searched refs:intel_de_write (Results 1 – 25 of 45) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c467 intel_de_write(display, dsc_reg[i], pps_val); in intel_dsc_pps_write()
585 intel_de_write(display, DSCA_RC_BUF_THRESH_0, in intel_dsc_pps_configure()
587 intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW, in intel_dsc_pps_configure()
589 intel_de_write(display, DSCA_RC_BUF_THRESH_1, in intel_dsc_pps_configure()
591 intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW, in intel_dsc_pps_configure()
594 intel_de_write(display, DSCC_RC_BUF_THRESH_0, in intel_dsc_pps_configure()
596 intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW, in intel_dsc_pps_configure()
598 intel_de_write(display, DSCC_RC_BUF_THRESH_1, in intel_dsc_pps_configure()
600 intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW, in intel_dsc_pps_configure()
604 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe), in intel_dsc_pps_configure()
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H A Dintel_vrr.c320 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
322 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
324 intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
622 intel_de_write(display, in intel_vrr_set_transcoder_timings()
628 intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
630 intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
632 intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
634 intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
641 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
645 intel_de_write(display, in intel_vrr_set_transcoder_timings()
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H A Dintel_fdi.c410 intel_de_write(display, SOUTH_CHICKEN1, temp); in cpt_set_fdi_bc_bifurcation()
455 intel_de_write(display, reg, temp); in intel_fdi_normal_train()
466 intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); in intel_fdi_normal_train()
490 intel_de_write(display, FDI_RX_TUSIZE1(pipe), in ilk_fdi_link_train()
502 intel_de_write(display, reg, temp); in ilk_fdi_link_train()
513 intel_de_write(display, reg, temp | FDI_TX_ENABLE); in ilk_fdi_link_train()
519 intel_de_write(display, reg, temp | FDI_RX_ENABLE); in ilk_fdi_link_train()
525 intel_de_write(display, FDI_RX_CHICKEN(pipe), in ilk_fdi_link_train()
527 intel_de_write(display, FDI_RX_CHICKEN(pipe), in ilk_fdi_link_train()
537 intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK); in ilk_fdi_link_train()
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H A Dvlv_dsi.c114 intel_de_write(display, reg, val); in write_data()
175 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
185 intel_de_write(display, ctrl_reg, in intel_dsi_host_transfer()
239 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
246 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); in dpi_send_cmd()
450 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); in bxt_dsi_device_ready()
453 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); in bxt_dsi_device_ready()
476 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_device_ready()
487 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_device_ready()
491 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_device_ready()
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H A Dintel_flipq.c185 intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe), in intel_flipq_write_tail()
197 intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE); in intel_flipq_sw_dmc_wake()
259 intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0); in intel_flipq_reset()
261 intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0); in intel_flipq_reset()
262 intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0); in intel_flipq_reset()
267 intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0); in intel_flipq_reset()
268 intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0); in intel_flipq_reset()
273 intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0); in intel_flipq_reset()
296 intel_de_write(display, PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr), in intel_flipq_enable()
298 intel_de_write(display, PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr), in intel_flipq_enable()
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H A Di9xx_display_sr.c47 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
48 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
51 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
54 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
57 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
58 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
61 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
96 intel_de_write(display, DSPARB(display), display->restore.saveDSPARB); in i9xx_display_sr_restore()
H A Dintel_display_irq.c35 intel_de_write(display, regs.imr, 0xffffffff); in irq_reset()
38 intel_de_write(display, regs.ier, 0); in irq_reset()
41 intel_de_write(display, regs.iir, 0xffffffff); in irq_reset()
43 intel_de_write(display, regs.iir, 0xffffffff); in irq_reset()
60 intel_de_write(display, reg, 0xffffffff); in assert_iir_is_zero()
62 intel_de_write(display, reg, 0xffffffff); in assert_iir_is_zero()
71 intel_de_write(display, regs.ier, ier_val); in irq_init()
72 intel_de_write(display, regs.imr, imr_val); in irq_init()
78 intel_de_write(display, regs.emr, 0xffffffff); in error_reset()
81 intel_de_write(display, regs.eir, 0xffffffff); in error_reset()
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H A Dintel_tv.c1403 intel_de_write(display, TV_H_CTL_1, hctl1); in set_tv_mode_timings()
1404 intel_de_write(display, TV_H_CTL_2, hctl2); in set_tv_mode_timings()
1405 intel_de_write(display, TV_H_CTL_3, hctl3); in set_tv_mode_timings()
1406 intel_de_write(display, TV_V_CTL_1, vctl1); in set_tv_mode_timings()
1407 intel_de_write(display, TV_V_CTL_2, vctl2); in set_tv_mode_timings()
1408 intel_de_write(display, TV_V_CTL_3, vctl3); in set_tv_mode_timings()
1409 intel_de_write(display, TV_V_CTL_4, vctl4); in set_tv_mode_timings()
1410 intel_de_write(display, TV_V_CTL_5, vctl5); in set_tv_mode_timings()
1411 intel_de_write(display, TV_V_CTL_6, vctl6); in set_tv_mode_timings()
1412 intel_de_write(display, TV_V_CTL_7, vctl7); in set_tv_mode_timings()
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H A Dintel_pch_display.c134 intel_de_write(display, hdmi_reg, val); in ibx_sanitize_pch_hdmi_port()
153 intel_de_write(display, dp_reg, val); in ibx_sanitize_pch_dp_port()
229 intel_de_write(display, PCH_TRANS_HTOTAL(pch_transcoder), in ilk_pch_transcoder_set_timings()
231 intel_de_write(display, PCH_TRANS_HBLANK(pch_transcoder), in ilk_pch_transcoder_set_timings()
233 intel_de_write(display, PCH_TRANS_HSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
236 intel_de_write(display, PCH_TRANS_VTOTAL(pch_transcoder), in ilk_pch_transcoder_set_timings()
238 intel_de_write(display, PCH_TRANS_VBLANK(pch_transcoder), in ilk_pch_transcoder_set_timings()
240 intel_de_write(display, PCH_TRANS_VSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
242 intel_de_write(display, PCH_TRANS_VSYNCSHIFT(pch_transcoder), in ilk_pch_transcoder_set_timings()
272 intel_de_write(display, reg, val); in ilk_enable_pch_transcoder()
[all …]
H A Dintel_backlight.c219 intel_de_write(display, BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
229 intel_de_write(display, BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
259 intel_de_write(display, BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
270 intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
279 intel_de_write(display, BXT_BLC_PWM_DUTY(panel->backlight.controller), level); in bxt_set_backlight()
362 intel_de_write(display, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in lpt_disable_backlight()
489 intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); in lpt_enable_backlight()
502 intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2); in lpt_enable_backlight()
512 intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); in lpt_enable_backlight()
514 intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); in lpt_enable_backlight()
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H A Dintel_casf.c71 intel_de_write(display, SHRPLUT_INDEX(crtc->pipe), in intel_casf_filter_lut_load()
75 intel_de_write(display, SHRPLUT_DATA(crtc->pipe), in intel_casf_filter_lut_load()
276 intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl); in intel_casf_enable()
286 intel_de_write(display, SKL_PS_CTRL(crtc->pipe, 1), 0); in intel_casf_disable()
287 intel_de_write(display, SKL_PS_WIN_POS(crtc->pipe, 1), 0); in intel_casf_disable()
288 intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0); in intel_casf_disable()
289 intel_de_write(display, SKL_PS_WIN_SZ(crtc->pipe, 1), 0); in intel_casf_disable()
H A Dintel_crt.c203 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); in intel_crt_set_dpms()
220 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_set_dpms()
499 intel_de_write(display, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
509 intel_de_write(display, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
554 intel_de_write(display, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
560 intel_de_write(display, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
618 intel_de_write(display, PORT_HOTPLUG_STAT(display), in intel_crt_detect_hotplug()
724 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050); in intel_crt_load_detect()
730 intel_de_write(display, TRANSCONF(display, cpu_transcoder), in intel_crt_load_detect()
744 intel_de_write(display, TRANSCONF(display, cpu_transcoder), in intel_crt_load_detect()
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H A Dicl_dsi.c184 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp); in dsi_send_pkt_payld()
221 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp); in dsi_send_pkt_hdr()
269 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
279 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
341 intel_de_write(display, dss_ctl1_reg, dss_ctl1); in configure_dual_link_mode()
381 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port), in gen11_dsi_program_esc_clk_div()
387 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port), in gen11_dsi_program_esc_clk_div()
394 intel_de_write(display, ADL_MIPIO_DW(port, 8), in gen11_dsi_program_esc_clk_div()
464 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
476 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), in gen11_dsi_config_phy_lanes_sequence()
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H A Dintel_dp_test.c234 intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0); in intel_dp_phy_pattern_update()
242 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
248 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
254 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
266 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val); in intel_dp_phy_pattern_update()
268 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val); in intel_dp_phy_pattern_update()
270 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val); in intel_dp_phy_pattern_update()
271 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
284 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
296 intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0); in intel_dp_phy_pattern_update()
H A Dg4x_dp.c215 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
230 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
248 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_off()
428 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
448 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
452 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
478 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_dp_audio_enable()
497 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_dp_audio_disable()
599 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in cpt_set_link_train()
612 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in cpt_set_idle_link_train()
[all …]
H A Dintel_fbc.c337 intel_de_write(display, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
355 intel_de_write(display, FBC_TAG(i), 0); in i8xx_fbc_activate()
358 intel_de_write(display, FBC_CONTROL2, in i8xx_fbc_activate()
360 intel_de_write(display, FBC_FENCE_OFF, in i8xx_fbc_activate()
364 intel_de_write(display, FBC_CONTROL, in i8xx_fbc_activate()
401 intel_de_write(display, FBC_CFB_BASE, in i8xx_fbc_program_cfb()
403 intel_de_write(display, FBC_LL_BASE, in i8xx_fbc_program_cfb()
477 intel_de_write(display, DPFC_FENCE_YOFF, in g4x_fbc_activate()
480 intel_de_write(display, DPFC_CONTROL, in g4x_fbc_activate()
493 intel_de_write(display, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
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H A Dintel_hdcp.c370 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); in intel_hdcp_clear_keys()
371 intel_de_write(display, HDCP_KEY_STATUS, in intel_hdcp_clear_keys()
409 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); in intel_hdcp_load_keys()
421 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); in intel_hdcp_load_keys()
429 intel_de_write(display, HDCP_SHA_TEXT, sha_text); in intel_write_sha_text()
496 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); in intel_hdcp_validate_v_prime()
513 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
532 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
565 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
574 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
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H A Dintel_combo_phy.c90 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
91 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
347 intel_de_write(display, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
355 intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
360 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
H A Dvlv_dsi_pll.c384 intel_de_write(display, MIPI_CTRL(display, port), in vlv_dsi_reset_clocks()
427 intel_de_write(display, MIPIO_TXESC_CLK_DIV1, in glk_dsi_program_esc_clock()
429 intel_de_write(display, MIPIO_TXESC_CLK_DIV2, in glk_dsi_program_esc_clock()
483 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
556 intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
593 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
599 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); in bxt_dsi_reset_clocks()
H A Dintel_dkl_phy.c32 intel_de_write(display, in dkl_phy_set_hip_idx()
75 intel_de_write(display, DKL_REG_MMIO(reg), val); in intel_dkl_phy_write()
H A Dintel_display_power_well.c691 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
702 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
950 intel_de_write(display, regs->driver, drv_req | mask); in hsw_power_well_sync_hw()
951 intel_de_write(display, regs->bios, bios_req & ~mask); in hsw_power_well_sync_hw()
1232 intel_de_write(display, MI_ARB_VLV, in vlv_init_display_clock_gating()
1234 intel_de_write(display, CBR1_VLV, 0); in vlv_init_display_clock_gating()
1237 intel_de_write(display, RAWCLK_FREQ_VLV, in vlv_init_display_clock_gating()
1262 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_init()
1516 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_enable()
1546 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_disable()
[all …]
H A Dintel_pch_refclk.c118 intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE); in lpt_disable_iclkip()
234 intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_UNGATE); in lpt_program_iclkip()
622 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
641 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
652 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
666 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
H A Dintel_alpm.c328 intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), in lnl_alpm_configure()
344 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl); in lnl_alpm_configure()
380 intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val); in intel_alpm_port_configure()
382 intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val); in intel_alpm_port_configure()
416 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0); in intel_alpm_pre_plane_update()
H A Dintel_lpe_audio.c239 intel_de_write(display, VLV_AUD_CHICKEN_BIT_REG, in lpe_audio_setup()
350 intel_de_write(display, VLV_AUD_PORT_EN_DBG(port), in intel_lpe_audio_notify()
359 intel_de_write(display, VLV_AUD_PORT_EN_DBG(port), in intel_lpe_audio_notify()
H A Dintel_display.c488 intel_de_write(display, TRANSCONF(display, cpu_transcoder), in intel_enable_transcoder()
539 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); in intel_disable_transcoder()
715 intel_de_write(display, PIPE_CHICKEN(pipe), tmp); in icl_set_pipe_chicken()
1586 intel_de_write(display, WM_LINETIME(crtc->pipe), in hsw_set_linetime_wm()
1619 intel_de_write(display, TRANS_MULT(display, cpu_transcoder), in hsw_configure_cpu_transcoder()
2051 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); in valleyview_crtc_enable()
2054 intel_de_write(display, CHV_BLEND(display, pipe), in valleyview_crtc_enable()
2056 intel_de_write(display, CHV_CANVAS(display, pipe), 0); in valleyview_crtc_enable()
2584 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); in intel_set_m_n()
2585 intel_de_write(display, data_n_reg, m_n->data_n); in intel_set_m_n()
[all …]

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