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Searched refs:intel_de_read (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c42 cur_state = intel_de_read(display, in assert_fdi_tx()
45 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
67 cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
95 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; in assert_fdi_tx_pll_enabled()
105 cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; in assert_fdi_rx_pll()
274 fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; in intel_fdi_pll_freq_update()
393 temp = intel_de_read(display, SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
398 intel_de_read(display, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
401 intel_de_read(display, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
447 temp = intel_de_read(display, reg); in intel_fdi_normal_train()
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H A Dintel_pch_display.c111 val = intel_de_read(display, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
121 u32 val = intel_de_read(display, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
140 u32 val = intel_de_read(display, dp_reg); in ibx_sanitize_pch_dp_port()
230 intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
232 intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
234 intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
237 intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
239 intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
241 intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
243 intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
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H A Di9xx_display_sr.c22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
36 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
74 display->restore.saveDSPARB = intel_de_read(display, DSPARB(display)); in i9xx_display_sr_save()
H A Dintel_crt.c96 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
133 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
491 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
515 adpa = intel_de_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
548 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); in valleyview_crt_detect_hotplug()
564 adpa = intel_de_read(display, crt->adpa_reg); in valleyview_crt_detect_hotplug()
613 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display)); in intel_crt_detect_hotplug()
710 save_bclrpat = intel_de_read(display, in intel_crt_load_detect()
712 save_vtotal = intel_de_read(display, in intel_crt_load_detect()
714 vblank = intel_de_read(display, in intel_crt_load_detect()
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H A Dintel_backlight.c154 return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
161 return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
170 val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
192 return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in vlv_get_backlight()
200 return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
218 val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
228 tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
258 tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
269 tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
358 tmp = intel_de_read(display, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
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H A Dintel_combo_phy.c62 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
98 u32 val = intel_de_read(display, reg); in check_phy_reg()
156 return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
158 return !(intel_de_read(display, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
160 (intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
337 val = intel_de_read(display, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
351 val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
357 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
H A Dintel_vrr.c610 … !(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE)); in intel_vrr_set_transcoder_timings()
753 return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; in intel_vrr_is_push_sent()
805 u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); in intel_vrr_enable_dc_balancing()
856 u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); in intel_vrr_disable_dc_balancing()
992 reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)); in intel_vrr_get_dc_balance_config()
995 reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)); in intel_vrr_get_dc_balance_config()
999 intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe)); in intel_vrr_get_dc_balance_config()
1001 intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe)); in intel_vrr_get_dc_balance_config()
1003 intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe)); in intel_vrr_get_dc_balance_config()
1005 intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe)); in intel_vrr_get_dc_balance_config()
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H A Dintel_display_power_well.c329 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
330 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
332 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
333 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
626 val = intel_de_read(display, regs->driver); in hsw_power_well_enabled()
636 val |= intel_de_read(display, regs->bios); in hsw_power_well_enabled()
644 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), in assert_can_enable_dc9()
647 intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc9()
651 intel_de_read(display, HSW_PWR_WELL_CTL2) & in assert_can_enable_dc9()
671 intel_de_read(display, DC_STATE_EN) & in assert_can_disable_dc9()
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H A Dintel_display_irq.c52 u32 val = intel_de_read(display, reg); in assert_iir_is_zero()
208 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
273 u32 sdeimr = intel_de_read(display, SDEIMR); in ibx_display_interrupt_update()
482 intel_de_read(display, PIPE_CRC_RES_HSW(pipe)), in hsw_pipe_crc_irq_handler()
490 intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
491 intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
492 intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
493 intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
494 intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
503 res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe)); in i9xx_pipe_crc_irq_handler()
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H A Dvlv_dsi.c125 u32 val = intel_de_read(display, reg); in read_data()
242 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) in dpi_send_cmd()
347 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); in glk_dsi_enable_io()
363 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); in glk_dsi_enable_io()
387 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { in glk_dsi_device_ready()
448 val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); in bxt_dsi_device_ready()
638 temp = intel_de_read(display, port_ctrl); in intel_dsi_port_enable()
962 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; in intel_dsi_get_hw_state()
971 enabled = intel_de_read(display, in intel_dsi_get_hw_state()
976 u32 tmp = intel_de_read(display, in intel_dsi_get_hw_state()
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H A Dicl_dsi.c63 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
70 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
202 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
266 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); in dsi_program_swing_and_deemphasis()
276 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); in dsi_program_swing_and_deemphasis()
314 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); in configure_dual_link_mode()
461 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); in gen11_dsi_config_phy_lanes_sequence()
472 tmp = intel_de_read(display, in gen11_dsi_config_phy_lanes_sequence()
492 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); in gen11_dsi_voltage_swing_program_seq()
509 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); in gen11_dsi_voltage_swing_program_seq()
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H A Dintel_flipq.c178 return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)); in intel_flipq_current_head()
221 intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i))); in intel_flipq_dump()
229 intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)), in intel_flipq_dump()
230 intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id))); in intel_flipq_dump()
240 intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe))); in intel_flipq_dump()
242 tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe)); in intel_flipq_dump()
433 pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)); in intel_flipq_add()
H A Dintel_tc.c275 lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); in get_lane_mask()
314 val = intel_de_read(display, reg); in get_pin_assignment()
438 val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia)); in intel_tc_port_set_fia_lane_count()
533 fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); in icl_tc_phy_hpd_live_status()
534 pch_isr = intel_de_read(display, SDEISR); in icl_tc_phy_hpd_live_status()
570 val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia)); in icl_tc_phy_is_ready()
589 val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); in icl_tc_phy_take_ownership()
614 val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); in icl_tc_phy_is_owned()
777 val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1)); in tgl_tc_phy_init()
823 cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR); in adlp_tc_phy_hpd_live_status()
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H A Dintel_lvds.c92 val = intel_de_read(display, lvds_reg); in intel_lvds_port_enabled()
131 tmp = intel_de_read(display, lvds_encoder->reg); in intel_lvds_get_config()
149 tmp = intel_de_read(display, PFIT_CONTROL(display)); in intel_lvds_get_config()
162 pps->powerdown_on_reset = intel_de_read(display, in intel_lvds_pps_get_hw_state()
165 val = intel_de_read(display, PP_ON_DELAYS(display, 0)); in intel_lvds_pps_get_hw_state()
170 val = intel_de_read(display, PP_OFF_DELAYS(display, 0)); in intel_lvds_pps_get_hw_state()
174 val = intel_de_read(display, PP_DIVISOR(display, 0)); in intel_lvds_pps_get_hw_state()
216 val = intel_de_read(display, PP_CONTROL(display, 0)); in intel_lvds_pps_init_hw()
820 val = intel_de_read(display, lvds_encoder->reg); in compute_is_dual_link_lvds()
871 lvds = intel_de_read(display, lvds_reg); in intel_lvds_init()
H A Dg4x_dp.c125 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
175 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN; in assert_dp_port()
186 bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE; in assert_edp_pll()
259 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
283 val = intel_de_read(display, dp_reg); in g4x_dp_port_enabled()
350 tmp = intel_de_read(display, intel_dp->output_reg); in intel_dp_get_config()
355 u32 trans_dp = intel_de_read(display, in intel_dp_get_config()
395 if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ) in intel_dp_get_config()
421 (intel_de_read(display, intel_dp->output_reg) & in intel_dp_link_down()
686 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); in intel_enable_dp()
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H A Dintel_tv.c919 u32 tmp = intel_de_read(display, TV_CTL); in intel_tv_get_hw_state()
1106 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_get_config()
1107 hctl1 = intel_de_read(display, TV_H_CTL_1); in intel_tv_get_config()
1108 hctl3 = intel_de_read(display, TV_H_CTL_3); in intel_tv_get_config()
1109 vctl1 = intel_de_read(display, TV_V_CTL_1); in intel_tv_get_config()
1110 vctl2 = intel_de_read(display, TV_V_CTL_2); in intel_tv_get_config()
1145 tmp = intel_de_read(display, TV_WIN_POS); in intel_tv_get_config()
1149 tmp = intel_de_read(display, TV_WIN_SIZE); in intel_tv_get_config()
1452 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_pre_enable()
1578 intel_de_read(display, TV_DAC) & TV_DAC_SAVE); in intel_tv_pre_enable()
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H A Dintel_pch_refclk.c242 if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
405 u32 fuse_strap = intel_de_read(display, FUSE_STRAP); in spll_uses_pch_ssc()
406 u32 ctl = intel_de_read(display, SPLL_CTL); in spll_uses_pch_ssc()
424 u32 fuse_strap = intel_de_read(display, FUSE_STRAP); in wrpll_uses_pch_ssc()
425 u32 ctl = intel_de_read(display, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
541 temp = intel_de_read(display, PCH_DPLL(pll->info->id)); in ilk_init_pch_refclk()
562 val = intel_de_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
H A Dintel_overlay.c334 tmp = intel_de_read(display, DOVSTA); in intel_overlay_continue()
474 if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { in intel_overlay_release_old_vid()
952 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); in update_pfit_vscale_ratio()
959 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
960 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); in update_pfit_vscale_ratio()
962 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); in update_pfit_vscale_ratio()
1305 attrs->gamma0 = intel_de_read(display, OGAMC0); in intel_overlay_attrs_ioctl()
1306 attrs->gamma1 = intel_de_read(display, OGAMC1); in intel_overlay_attrs_ioctl()
1307 attrs->gamma2 = intel_de_read(display, OGAMC2); in intel_overlay_attrs_ioctl()
1308 attrs->gamma3 = intel_de_read(display, OGAMC3); in intel_overlay_attrs_ioctl()
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H A Dintel_display.c383 u32 val = intel_de_read(display, in assert_transcoder()
473 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); in intel_enable_transcoder()
519 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); in intel_disable_transcoder()
686 tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); in icl_set_pipe_chicken()
2558 bool bios_lvds_use_ssc = intel_de_read(display, in intel_panel_sanitize_ssc()
2845 return intel_de_read(display, in intel_pipe_is_interlaced()
2848 return intel_de_read(display, in intel_pipe_is_interlaced()
2860 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); in intel_get_transcoder_timings()
2865 tmp = intel_de_read(display, in intel_get_transcoder_timings()
2871 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); in intel_get_transcoder_timings()
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H A Dvlv_dsi_pll.c278 val = intel_de_read(display, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
292 val = intel_de_read(display, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
366 config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
382 temp = intel_de_read(display, MIPI_CTRL(display, port)); in vlv_dsi_reset_clocks()
447 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
588 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
H A Dintel_pfit.c626 ctl = intel_de_read(display, PF_CTL(crtc->pipe)); in ilk_pfit_get_config()
637 pos = intel_de_read(display, PF_WIN_POS(crtc->pipe)); in ilk_pfit_get_config()
638 size = intel_de_read(display, PF_WIN_SZ(crtc->pipe)); in ilk_pfit_get_config()
667 intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE); in i9xx_pfit_enable()
692 intel_de_read(display, PFIT_CONTROL(display))); in i9xx_pfit_disable()
715 tmp = intel_de_read(display, PFIT_CONTROL(display)); in i9xx_pfit_get_config()
730 intel_de_read(display, PFIT_PGM_RATIOS(display)); in i9xx_pfit_get_config()
H A Dintel_pmdemand.c418 reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0)); in intel_pmdemand_init_pmdemand_params()
420 reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); in intel_pmdemand_init_pmdemand_params()
455 return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & in intel_pmdemand_req_complete()
587 reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0)); in intel_pmdemand_program_params()
590 reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); in intel_pmdemand_program_params()
H A Dintel_dmc.c688 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); in assert_dmc_loaded()
698 found = intel_de_read(display, reg); in assert_dmc_loaded()
1584 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); in intel_dmc_update_dc6_allowed_count()
1658 intel_de_read(display, dc3co_reg)); in intel_dmc_debugfs_status_show()
1666 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); in intel_dmc_debugfs_status_show()
1673 intel_de_read(display, dc6_reg)); in intel_dmc_debugfs_status_show()
1676 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1680 intel_de_read(display, DMC_SSP_BASE)); in intel_dmc_debugfs_status_show()
1681 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); in intel_dmc_debugfs_status_show()
1702 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); in intel_pipedmc_irq_handler()
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H A Dintel_cdclk.c379 tmp = intel_de_read(display, display->platform.pineview || in intel_hpll_vco()
554 u32 lcpll = intel_de_read(display, LCPLL_CTL); in hsw_get_cdclk()
559 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
662 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
834 u32 lcpll = intel_de_read(display, LCPLL_CTL); in bdw_get_cdclk()
839 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
883 (intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
973 val = intel_de_read(display, LCPLL1_CTL); in skl_dpll0_update()
980 val = intel_de_read(display, DPLL_CTRL1); in skl_dpll0_update()
1018 cdctl = intel_de_read(display, CDCLK_CTL); in skl_get_cdclk()
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H A Dintel_dvo.c139 tmp = intel_de_read(display, DVO(port)); in intel_dvo_connector_get_hw_state()
154 tmp = intel_de_read(display, DVO(port)); in intel_dvo_get_hw_state()
170 tmp = intel_de_read(display, DVO(port)); in intel_dvo_get_config()
300 dvo_val = intel_de_read(display, DVO(port)) & in intel_dvo_pre_enable()

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