Home
last modified time | relevance | path

Searched refs:SW1 (Results 1 – 25 of 36) sorted by relevance

12

/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044c2-smarc.dts11 * DIP-Switch SW1 setting on SoM
13 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
16 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
17 * Please change below macros according to SW1 setting
40 * - Set DIP-Switch SW1-4 to Off position.
H A Dr9a07g043u11-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
22 * - Set DIP-Switch SW1-3 to On position.
H A Drzg2l-smarc-som.dtsi12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
260 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
263 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
264 * SW1[2] should be at position 3/ON to enable uSD card CN3
H A Drzg2lc-smarc-som.dtsi179 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
182 * SW1[2] should be at OFF position to enable 64 GB eMMC
183 * SW1[2] should be at position ON to enable uSD card CN3
H A Dr9a09g077m44-rzt2h-evk.dts47 * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
53 * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
H A Drzg2l-smarc.dtsi171 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
H A Drzg2lc-smarc.dtsi183 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f01-smarc.dts11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032-rzn1d400-db.dts37 label = "SW1-1";
44 label = "SW1-2";
51 label = "SW1-3";
58 label = "SW1-4";
65 label = "SW1-5";
72 label = "SW1-6";
79 label = "SW1-7";
86 label = "SW1-8";
H A Dr8a7779-marzen.dts64 label = "SW1-1";
71 label = "SW1-2";
87 label = "SW1-3";
93 label = "SW1-4";
H A Dr8a7742-iwg21d-q7-dbcm-ca.dts238 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
270 /* Set SW1 switch on the SOM to 'ON' */
H A Dr7s72100-rskrza1.dts83 label = "SW1";
/linux/Documentation/hid/
H A Dhid-alps.rst118 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
152 SW1-SW6:
168 Byte1 1 1 1 0 1 SW3 SW2 SW1
177 SW1-SW3:
/linux/Documentation/networking/
H A Darcnet-hardware.rst804 < | SW1 | | SW2 | |
830 SW1 1-6: I/O Base Address Select
890 The first six switches in switch group SW1 are used to select one
933 Switches seven through ten of switch group SW1 are used to select the
1064 SW1: DIP-Switches for Station Address
1086 The station address is binary-coded with SW1.
1342 | | 90C65 || SW1 | ____|
1420 The last three switches in switch block SW1 are used to select one
1443 Switches 1-5 of switch block SW1 select the Memory Base address.
1555 < | PROM | | SW1 | A | 2 | ID3
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
84 SW1 {
/linux/drivers/regulator/
H A Dpcap-regulator.c131 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
228 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
H A Dcpcap-regulator.c330 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
406 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
H A Dpv88060-regulator.c217 PV88060_SW(PV88060, SW1, 5000000),
H A Dltc3676.c225 LTC3676_LINEAR_REG(SW1, sw1, BUCK1, DVB1A),
H A Dltc3589.c254 LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
/linux/include/linux/mfd/
H A Dezx-pcap.h129 #define SW1 17 macro
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-qsrb.dts34 regulator-name = "SW1";
/linux/arch/arm/boot/dts/microchip/
H A Dat91-kizbox3-hs.dts72 label = "SW1";
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-odroid-n2.dtsi290 * The SW1 slide should also be set to the correct position.
/linux/arch/arm/boot/dts/st/
H A Dstm32mp151c-plyaqm.dts171 "", "", "", "", "", "", "", "SW1",

12