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Searched refs:SOC15_REG_OFFSET (Results 1 – 25 of 99) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c45 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACK… in jpeg_v1_0_decode_ring_patch_wreg()
64 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); in jpeg_v1_0_decode_ring_set_patch_ring()
70 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); in jpeg_v1_0_decode_ring_set_patch_ring()
82 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
88 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA); in jpeg_v1_0_decode_ring_set_patch_ring()
94 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
99 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_… in jpeg_v1_0_decode_ring_set_patch_ring()
101 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0… in jpeg_v1_0_decode_ring_set_patch_ring()
103 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ… in jpeg_v1_0_decode_ring_set_patch_ring()
121 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_set_patch_ring()
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H A Dnbio_v7_2.c111 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); in nbio_v7_2_sdma_doorbell_range()
133 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); in nbio_v7_2_vcn_doorbell_range()
191 u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE)); in nbio_v7_2_ih_doorbell_range()
206 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE), in nbio_v7_2_ih_doorbell_range()
238 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL)); in nbio_v7_2_update_medium_grain_clock_gating()
256 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data); in nbio_v7_2_update_medium_grain_clock_gating()
268 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); in nbio_v7_2_update_medium_grain_light_sleep()
275 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); in nbio_v7_2_update_medium_grain_light_sleep()
277 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, in nbio_v7_2_update_medium_grain_light_sleep()
287 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1), in nbio_v7_2_update_medium_grain_light_sleep()
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H A Damdgpu_amdkfd_gfx_v10.c110 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); in kgd_set_pasid_vmid_mapping()
111 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_set_pasid_vmid_mapping()
116 while (!(RREG32(SOC15_REG_OFFSET( in kgd_set_pasid_vmid_mapping()
123 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_set_pasid_vmid_mapping()
130 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_set_pasid_vmid_mapping()
165 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
173 SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
189 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
224 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
227 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
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H A Damdgpu_amdkfd_gfx_v11.c86 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_CONFIG), sh_mem_config); in program_sh_mem_settings_v11()
87 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v11()
100 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid, value); in set_pasid_vmid_mapping_v11()
134 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
138 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
187 value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS)); in hqd_load_v11()
190 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value); in hqd_load_v11()
195 hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_load_v11()
198 reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v11()
205 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v11()
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H A Dvega10_ih.c53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset()
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_init_register_offset()
59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega10_ih_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega10_ih_init_register_offset()
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega10_ih_init_register_offset()
67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in vega10_ih_init_register_offset()
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H A Dnavi10_ih.c55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset()
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in navi10_ih_init_register_offset()
61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in navi10_ih_init_register_offset()
62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in navi10_ih_init_register_offset()
68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in navi10_ih_init_register_offset()
69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in navi10_ih_init_register_offset()
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H A Dvega20_ih.c61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset()
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega20_ih_init_register_offset()
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega20_ih_init_register_offset()
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega20_ih_init_register_offset()
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega20_ih_init_register_offset()
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in vega20_ih_init_register_offset()
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H A Dimu_v12_0.c308 if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE)) in imu_v12_init_gfxhub_settings()
310 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP)) in imu_v12_init_gfxhub_settings()
312 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET)) in imu_v12_init_gfxhub_settings()
314 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE)) in imu_v12_init_gfxhub_settings()
316 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT)) in imu_v12_init_gfxhub_settings()
318 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP)) in imu_v12_init_gfxhub_settings()
320 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL)) in imu_v12_init_gfxhub_settings()
322 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR)) in imu_v12_init_gfxhub_settings()
324 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR)) in imu_v12_init_gfxhub_settings()
326 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START)) in imu_v12_init_gfxhub_settings()
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H A Damdgpu_amdkfd_arcturus.c81 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
89 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0, in get_sdma_rlc_reg_offset()
93 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0, in get_sdma_rlc_reg_offset()
97 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0, in get_sdma_rlc_reg_offset()
101 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0, in get_sdma_rlc_reg_offset()
105 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0, in get_sdma_rlc_reg_offset()
109 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0, in get_sdma_rlc_reg_offset()
328 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)); in set_barrier_auto_waitcnt()
331 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG), data); in set_barrier_auto_waitcnt()
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H A Damdgpu_amdkfd_gfx_v9.c120 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
123 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping()
129 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping()
134 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
137 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
140 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping()
146 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping()
151 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
198 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
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H A Dmxgpu_ai.c58 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
68 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
140 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
150 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
182 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
247 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
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H A Dumc_v6_7.c74 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0); in umc_v6_7_query_error_status_helper()
81 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0); in umc_v6_7_query_error_status_helper()
88 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0); in umc_v6_7_query_error_status_helper()
274 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); in umc_v6_7_query_correctable_error_count()
276 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); in umc_v6_7_query_correctable_error_count()
278 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_correctable_error_count()
316 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_correctable_error_count()
345 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_querry_uncorrectable_error_count()
371 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()
374 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()
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H A Damdgpu_amdkfd_gfx_v10_3.c104 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value); in set_pasid_vmid_mapping_v10_3()
143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
210 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3()
213 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v10_3()
264 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), in hqd_load_v10_3()
347 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_dump_v10_3()
348 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_dump_v10_3()
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H A Dhdp_v4_0.c51 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp()
92 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_update_clock_gating()
100 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in hdp_v4_0_update_clock_gating()
102 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in hdp_v4_0_update_clock_gating()
116 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating()
132 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_get_clockgating_state()
H A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
242 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
246 while (!(RREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
256 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
260 reg = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX)); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
266 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
268 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
270 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
272 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
274 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), reg); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
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H A Dnbio_v7_7.c68 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE); in nbio_v7_7_sdma_doorbell_range()
90 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); in nbio_v7_7_vcn_doorbell_range()
193 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); in nbio_v7_7_get_hdp_flush_req_offset()
198 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); in nbio_v7_7_get_hdp_flush_done_offset()
203 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); in nbio_v7_7_get_pcie_index_offset()
208 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); in nbio_v7_7_get_pcie_data_offset()
213 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); in nbio_v7_7_get_pcie_port_index_offset()
218 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); in nbio_v7_7_get_pcie_port_data_offset()
341 SOC15_REG_OFFSET(NBIO, 0, in nbio_v7_7_set_reg_remap()
H A Dpsp_v14_0.c115 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), in psp_v14_0_wait_for_bootloader()
232 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81), in psp_v14_0_bootloader_load_sos()
253 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), in psp_v14_0_ring_stop()
263 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), in psp_v14_0_ring_stop()
301 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), in psp_v14_0_ring_create()
307 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), in psp_v14_0_ring_create()
333 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), in psp_v14_0_ring_create()
398 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), in psp_v14_0_memory_training_send_msg()
551 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), in psp_v14_0_load_usbc_pd_fw()
589 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), in psp_v14_0_read_usbc_pd_fw()
[all …]
H A Damdgpu_amdkfd_gfx_v12.c85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
89 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
124 for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_dump_v12()
125 reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++) in hqd_dump_v12()
171 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v12()
172 WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd); in wave_control_execute_v12()
181 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v12()
347 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + in kgd_gfx_v12_set_address_watch()
351 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + in kgd_gfx_v12_set_address_watch()
H A Dvcn_v2_5.c325 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
327 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
329 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
331 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
333 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
1009 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
1116 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1145 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1176 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
1190 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
[all …]
H A Dpsp_v13_0.c167 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92) in psp_v13_0_bootloader_print_status()
188 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), in psp_v13_0_wait_for_vmbx_ready()
220 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), in psp_v13_0_wait_for_bootloader()
370 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_bootloader_load_sos()
394 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), in psp_v13_0_ring_stop()
404 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), in psp_v13_0_ring_stop()
442 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), in psp_v13_0_ring_create()
448 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), in psp_v13_0_ring_create()
474 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), in psp_v13_0_ring_create()
539 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), in psp_v13_0_memory_training_send_msg()
[all …]
H A Dumc_v8_14.c46 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt); in umc_v8_14_clear_error_count_per_channel()
69 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt); in umc_v8_14_query_correctable_error_count()
84 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt); in umc_v8_14_query_uncorrectable_error_count()
129 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCntSel); in umc_v8_14_err_cnt_init_per_channel()
131 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt); in umc_v8_14_err_cnt_init_per_channel()
H A Dnbio_v7_0.c70 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v7_0_sdma_doorbell_range()
71 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); in nbio_v7_0_sdma_doorbell_range()
87 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v7_0_vcn_doorbell_range()
240 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); in nbio_v7_0_get_hdp_flush_req_offset()
245 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); in nbio_v7_0_get_hdp_flush_done_offset()
250 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v7_0_get_pcie_index_offset()
255 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v7_0_get_pcie_data_offset()
297 SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2; in nbio_v7_0_set_reg_remap()
H A Dumc_v8_7.c187 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_clear_error_count_per_channel()
189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_clear_error_count_per_channel()
245 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_query_correctable_error_count()
247 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_query_correctable_error_count()
249 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_correctable_error_count()
288 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_querry_uncorrectable_error_count()
336 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_error_address()
338 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_7_query_error_address()
397 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_err_cnt_init_per_channel()
399 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_err_cnt_init_per_channel()
H A Dnbio_v2_3.c112 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v2_3_sdma_doorbell_range()
113 instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) : in nbio_v2_3_sdma_doorbell_range()
114 instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) : in nbio_v2_3_sdma_doorbell_range()
115 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE); in nbio_v2_3_sdma_doorbell_range()
137 u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) : in nbio_v2_3_vcn_doorbell_range()
138 SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v2_3_vcn_doorbell_range()
298 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); in nbio_v2_3_get_hdp_flush_req_offset()
303 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); in nbio_v2_3_get_hdp_flush_done_offset()
308 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v2_3_get_pcie_index_offset()
313 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v2_3_get_pcie_data_offset()
[all …]
H A Dpsp_v13_0_4.c80 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), in psp_v13_0_4_wait_for_bootloader()
185 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_4_bootloader_load_sos()
206 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), in psp_v13_0_4_ring_stop()
216 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), in psp_v13_0_4_ring_stop()
254 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), in psp_v13_0_4_ring_create()
260 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), in psp_v13_0_4_ring_create()
286 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), in psp_v13_0_4_ring_create()

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