Lines Matching refs:SOC15_REG_OFFSET

58 	return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,  in xgpu_ai_mailbox_peek_msg()
68 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,  in xgpu_ai_mailbox_rcv_msg()
140 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,  in xgpu_ai_mailbox_trans_msg()
144 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),  in xgpu_ai_mailbox_trans_msg()
146 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),  in xgpu_ai_mailbox_trans_msg()
148 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),  in xgpu_ai_mailbox_trans_msg()
150 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),  in xgpu_ai_mailbox_trans_msg()
182 				RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,  in xgpu_ai_send_access_requests()
243 	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));  in xgpu_ai_set_mailbox_ack_irq()
247 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);  in xgpu_ai_set_mailbox_ack_irq()
331 	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));  in xgpu_ai_set_mailbox_rcv_irq()
335 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);  in xgpu_ai_set_mailbox_rcv_irq()