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Searched refs:REG_UPDATE (Results 1 – 25 of 112) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/ !
H A Ddcn20_mmhubbub.c83 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); in mmhubbub2_config_mcif_buf()
86 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub2_config_mcif_buf()
87 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
89 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
92 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub2_config_mcif_buf()
93 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub2_config_mcif_buf()
95 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0); in mmhubbub2_config_mcif_buf()
98 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub2_config_mcif_buf()
99 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
101 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/ !
H A Ddcn32_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub32_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub32_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub32_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub32_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub32_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub32_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/ !
H A Ddcn30_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub3_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub3_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
[all …]
H A Ddcn30_vpg.c79 REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); in vpg3_update_generic_info_packet()
82 REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, in vpg3_update_generic_info_packet()
113 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
117 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
121 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
125 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
129 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
133 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
137 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
141 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/ !
H A Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
127 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/ !
H A Ddcn30_dio_stream_encoder.c85 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
92 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
99 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
106 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
113 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
120 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
127 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
134 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
141 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, in enc3_update_hdmi_info_packet()
148 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, in enc3_update_hdmi_info_packet()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ !
H A Ddcn35_dccg.c147 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
150 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
153 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
156 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
246 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
250 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
254 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
258 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
262 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
283 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn401/ !
H A Ddcn401_dio_stream_encoder.c88 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc401_stream_encoder_dvi_set_stream_attribute()
128 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc401_stream_encoder_hdmi_set_stream_attribute()
152 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc401_stream_encoder_hdmi_set_stream_attribute()
215 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); in enc401_stream_encoder_hdmi_set_stream_attribute()
218 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc401_stream_encoder_hdmi_set_stream_attribute()
225 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, in enc401_stream_encoder_hdmi_set_stream_attribute()
229 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); in enc401_stream_encoder_hdmi_set_stream_attribute()
240 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1); in enc401_set_dig_input_mode()
243 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2); in enc401_set_dig_input_mode()
246 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3); in enc401_set_dig_input_mode()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/ !
H A Ddce_stream_encoder.c74 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
99 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
H A Ddce_dmcu.c113 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); in dce_get_dmcu_psr_state()
126 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); in dce_get_dmcu_psr_state()
145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
152 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
207 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
224 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ !
H A Ddcn30_dwb.c76 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1); in dwb3_config_fc()
77 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x); in dwb3_config_fc()
78 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y); in dwb3_config_fc()
79 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb3_config_fc()
80 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb3_config_fc()
82 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0); in dwb3_config_fc()
86 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate); in dwb3_config_fc()
97 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1); in dwb3_enable()
111 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb3_enable()
114 REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96); in dwb3_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/ !
H A Ddcn35_dio_stream_encoder.c76 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc35_stream_encoder_dvi_set_stream_attribute()
115 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc35_stream_encoder_hdmi_set_stream_attribute()
140 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc35_stream_encoder_hdmi_set_stream_attribute()
203 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); in enc35_stream_encoder_hdmi_set_stream_attribute()
207 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc35_stream_encoder_hdmi_set_stream_attribute()
214 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, in enc35_stream_encoder_hdmi_set_stream_attribute()
218 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); in enc35_stream_encoder_hdmi_set_stream_attribute()
221 REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1); in enc35_stream_encoder_hdmi_set_stream_attribute()
224 REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0); in enc35_stream_encoder_hdmi_set_stream_attribute()
227 REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0); in enc35_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/ !
H A Ddcn20_stream_encoder.c84 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
91 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
98 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
105 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
112 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
119 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
126 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
133 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
152 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); in enc2_stream_encoder_update_hdmi_info_packets()
228 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1); in enc2_update_gsp7_128_info_packet()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/ !
H A Ddcn31_hpo_dp_stream_encoder.c66 REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
70 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
78 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
86 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
97 REG_UPDATE(DP_STREAM_ENC_INPUT_MUX_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
101 REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
105 REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
110 REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
115 REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
119 REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ !
H A Ddcn10_stream_encoder.c68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in enc1_update_generic_info_packet()
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in enc1_update_generic_info_packet()
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_update_generic_info_packet()
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ !
H A Ddcn401_dccg.c63 REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable); in dcn401_set_dppclk_enable()
66 REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable); in dcn401_set_dppclk_enable()
69 REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable); in dcn401_set_dppclk_enable()
72 REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable); in dcn401_set_dppclk_enable()
183 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
189 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
195 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
201 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
227 REG_UPDATE(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
236 REG_UPDATE(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/ !
H A Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/ !
H A Ddcn35_hubp.c45 REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable); in hubp35_set_fgcg()
85 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
89 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
94 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
100 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
105 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
110 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
115 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
119 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
123 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp35_program_pixel_format()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/ !
H A Ddcn32_dio_stream_encoder.c59 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, two_pixel_per_cyle ? 1 : 0); in enc32_dp_set_odm_combine()
88 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc32_stream_encoder_dvi_set_stream_attribute()
128 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc32_stream_encoder_hdmi_set_stream_attribute()
152 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
215 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
219 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc32_stream_encoder_hdmi_set_stream_attribute()
226 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, in enc32_stream_encoder_hdmi_set_stream_attribute()
230 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
278 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); in enc32_stream_encoder_dp_unblank()
284 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); in enc32_stream_encoder_dp_unblank()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ !
H A Ddcn20_dpp.c83 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); in dpp2_power_on_obuf()
85 REG_UPDATE(OBUF_MEM_PWR_CTRL, in dpp2_power_on_obuf()
88 REG_UPDATE(DSCL_MEM_PWR_CTRL, in dpp2_power_on_obuf()
124 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
126 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
127 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
221 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp2_cnv_setup()
222 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp2_cnv_setup()
223 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp2_cnv_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/ !
H A Ddcn314_dio_stream_encoder.c58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc314_reset_fifo()
71 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc314_enable_fifo()
76 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc314_enable_fifo()
83 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); in enc314_disable_fifo()
101 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine); in enc314_dp_set_odm_combine()
130 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc314_stream_encoder_dvi_set_stream_attribute()
170 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc314_stream_encoder_hdmi_set_stream_attribute()
194 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc314_stream_encoder_hdmi_set_stream_attribute()
257 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); in enc314_stream_encoder_hdmi_set_stream_attribute()
261 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc314_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/ !
H A Dhw_gpio.c54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
55 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
56 REG_UPDATE(EN_reg, EN, gpio->store.en); in restore_registers()
107 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
114 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
151 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
157 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
163 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ !
H A Ddcn31_dccg.c75 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
78 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
105 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
109 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
113 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
117 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
141 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
145 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
149 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
153 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ !
H A Ddcn20_optc.c59 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc2_enable_crtc()
63 REG_UPDATE(CONTROL, in optc2_enable_crtc()
114 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
117 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
120 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
139 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, in optc2_set_dsc_config()
145 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_dsc_config()
174 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
213 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_odm_combine()
249 REG_UPDATE(DWB_SOURCE_SELECT, in optc2_set_dwb_source()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce120/ !
H A Ddce120_hwseq.c206 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
209 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
212 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
217 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
220 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
223 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
228 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
231 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
234 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()

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