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Searched refs:REG_GENMASK (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_snps_phy_regs.h23 #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
24 #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
25 #define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
26 #define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
32 #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
33 #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
34 #define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
38 #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
44 #define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
47 #define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
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H A Dvlv_dpio_phy_regs.h27 #define DPIO_S1_DIV_MASK REG_GENMASK(30, 28)
33 #define DPIO_K_DIV_MASK REG_GENMASK(27, 24)
35 #define DPIO_P1_DIV_MASK REG_GENMASK(23, 21)
37 #define DPIO_P2_DIV_MASK REG_GENMASK(20, 16)
39 #define DPIO_N_DIV_MASK REG_GENMASK(15, 12)
42 #define DPIO_M1_DIV_MASK REG_GENMASK(10, 8)
44 #define DPIO_M2_DIV_MASK REG_GENMASK(7, 0)
49 #define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24)
50 #define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */
51 #define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16)
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H A Dintel_psr_regs.h15 #define EXITLINE_MASK REG_GENMASK(12, 0)
32 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25)
37 #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)
39 #define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16)
46 #define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)
51 #define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)
53 #define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)
58 #define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
74 #define TGL_PSR_MASK REG_GENMASK(2, 0)
106 #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)
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H A Dintel_color_regs.h16 #define PALETTE_RED_MASK REG_GENMASK(23, 16)
17 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
18 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
20 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
21 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
22 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
24 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
25 #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
26 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
27 #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
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H A Dskl_watermark_regs.h15 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
17 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
20 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
24 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
26 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
28 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
40 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
43 #define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16, 13)
45 #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
67 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
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H A Dintel_vdsc_regs.h39 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
93 #define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
95 #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
97 #define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
99 #define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
103 #define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
107 #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
108 #define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
113 #define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16)
114 #define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0)
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H A Dintel_sprite_regs.h16 #define DVS_FORMAT_MASK REG_GENMASK(26, 25)
25 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
46 #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
48 #define DVS_POS_X_MASK REG_GENMASK(15, 0)
54 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
56 #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
70 #define DVS_ADDR_MASK REG_GENMASK(31, 12)
79 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
81 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
96 #define DVS_FILTER_MASK REG_GENMASK(30, 29)
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H A Dintel_pfit_regs.h12 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
14 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
19 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
23 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
26 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
32 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
34 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
36 #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
37 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
47 #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
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H A Dbxt_dpio_phy_regs.h47 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
49 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
68 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
71 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
74 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
79 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
81 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
83 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
86 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
89 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
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H A Dintel_dsb_regs.h27 #define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8)
29 #define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0)
33 #define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23)
35 #define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15)
42 #define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27)
44 #define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23)
45 #define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20)
47 #define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17)
49 #define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13)
50 #define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7)
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H A Dintel_combo_phy_regs.h29 #define SUS_CLOCK_CONFIG REG_GENMASK(1, 0)
32 #define PG_SEQ_DELAY_OVERRIDE_MASK REG_GENMASK(26, 25)
34 #define PWR_DOWN_LN_MASK REG_GENMASK(7, 4)
60 #define PROCESS_INFO_MASK REG_GENMASK(28, 26)
64 #define VOLTAGE_INFO_MASK REG_GENMASK(25, 24)
89 #define DCC_MODE_SELECT_MASK REG_GENMASK(21, 20)
92 #define LATENCY_OPTIM_MASK REG_GENMASK(3, 2)
112 #define SWING_SEL_LOWER_MASK REG_GENMASK(13, 11)
114 #define FRC_LATENCY_OPTIM_MASK REG_GENMASK(10, 8)
116 #define RCOMP_SCALAR_MASK REG_GENMASK(7, 0)
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H A Dintel_pps_regs.h30 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
35 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
48 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
50 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
58 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
64 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
65 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
69 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
70 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
74 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
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H A Dintel_cursor_regs.h16 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
18 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
25 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
27 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
49 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
52 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
60 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
62 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
68 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
83 #define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
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H A Di9xx_plane_regs.h18 #define DISP_FORMAT_MASK REG_GENMASK(29, 26)
34 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
59 #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
61 #define DISP_POS_X_MASK REG_GENMASK(15, 0)
66 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
68 #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
73 #define DISP_ADDR_MASK REG_GENMASK(31, 12)
77 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
79 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
94 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
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H A Dskl_universal_plane_regs.h39 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
48 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
49 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
68 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
74 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
83 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
92 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
96 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
109 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
119 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
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H A Dintel_vga_regs.h18 #define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */
22 #define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */
31 #define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */
32 #define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */
33 #define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6)
34 #define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0)
H A Di9xx_wm_regs.h222 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
223 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
224 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
232 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
233 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
234 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
235 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
236 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
246 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
H A Dintel_lvds_regs.h21 #define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
35 #define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8)
43 #define LVDS_A3_POWER_MASK REG_GENMASK(7, 6)
50 #define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4)
58 #define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2)
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h21 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
22 #define MTL_CC_MASK REG_GENMASK(12, 9)
26 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
31 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
38 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
39 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
45 #define GMD_ID_SUBIP_FLAG_MASK REG_GENMASK(13, 6)
46 #define GMD_ID_REVID REG_GENMASK(5, 0)
57 #define MCR_SLICE_MASK REG_GENMASK(30, 27)
59 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24)
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H A Dxe_mchbar_regs.h31 #define PKG_PWR_UNIT REG_GENMASK(3, 0)
32 #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
33 #define PKG_TIME_UNIT REG_GENMASK(19, 16)
38 #define TEMP_MASK REG_GENMASK(7, 0)
41 #define PWR_LIM_VAL REG_GENMASK(14, 0)
43 #define PWR_LIM REG_GENMASK(15, 0)
44 #define PWR_LIM_TIME REG_GENMASK(23, 17)
45 #define PWR_LIM_TIME_X REG_GENMASK(23, 22)
46 #define PWR_LIM_TIME_Y REG_GENMASK(21, 17)
H A Dxe_engine_regs.h47 #define ENGINE_INSTANCE_ID REG_GENMASK(9, 4)
48 #define ENGINE_CLASS_ID REG_GENMASK(2, 0)
51 #define TAIL_ADDR REG_GENMASK(20, 3)
54 #define HEAD_ADDR REG_GENMASK(20, 2)
69 #define IDLE_WAIT_TIME REG_GENMASK(19, 0)
102 #define SELECTIVE_READ_GROUP REG_GENMASK(29, 23)
103 #define SELECTIVE_READ_INSTANCE REG_GENMASK(22, 16)
112 #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8)
113 #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1)
140 #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9)
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H A Dxe_regs.h29 #define TILE_COUNT REG_GENMASK(15, 8)
32 #define GMS_MASK REG_GENMASK(15, 8)
33 #define GGMS_MASK REG_GENMASK(7, 6)
51 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
52 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
55 #define MTL_RPA_MASK REG_GENMASK(8, 0)
58 #define MTL_RPE_MASK REG_GENMASK(8, 0)
H A Dxe_eu_stall_regs.h12 #define XEHPC_EUSTALL_BASE_BUF_ADDR REG_GENMASK(31, 6)
13 #define XEHPC_EUSTALL_BASE_XECORE_BUF_SZ REG_GENMASK(5, 3)
19 #define XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK REG_GENMASK(15, 2)
23 #define XEHPC_EUSTALL_REPORT1_READ_PTR_MASK REG_GENMASK(15, 2)
26 #define EUSTALL_MOCS REG_GENMASK(9, 3)
27 #define EUSTALL_SAMPLE_RATE REG_GENMASK(2, 0)
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h26 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
29 #define MTL_CC_MASK REG_GENMASK(10, 9)
33 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
41 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
80 #define MTL_MCR_GROUPID REG_GENMASK(11, 8)
81 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
293 #define VERT_WM_VAL REG_GENMASK(9, 0)
326 #define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */
327 #define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */
329 #define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
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/linux/drivers/gpu/drm/i915/
H A Di915_reg.h296 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
360 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
587 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
592 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
737 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
738 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
742 #define MTL_RPE_MASK REG_GENMASK(8, 0)
754 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
960 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
965 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
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