Home
last modified time | relevance | path

Searched refs:REG_BIT (Results 1 – 25 of 54) sorted by relevance

123

/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h56 #define MCR_MULTICAST REG_BIT(31)
71 #define LE_SCF_MASK REG_BIT(14)
77 #define LE_RSC_MASK REG_BIT(7)
79 #define LE_AOM_MASK REG_BIT(6)
92 #define EN_CMP_1WCOH REG_BIT(15)
93 #define CG_DIS_CNTLBUS REG_BIT(6)
101 #define AUX_INV REG_BIT(0)
108 #define EN_CMP_1WCOH_GW REG_BIT(14)
114 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
117 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
[all …]
H A Dxe_engine_regs.h64 #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
65 #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
66 #define IDLE_MSG_DISABLE REG_BIT(0)
96 #define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13)
101 #define SELECTIVE_READ_ADDRESSING REG_BIT(30)
116 #define GHWSP_CSB_REPORT_DIS REG_BIT(15)
117 #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14)
118 #define CS_PRIORITY_MEM_READ REG_BIT(7)
121 #define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
124 #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
[all …]
H A Dxe_gsc_regs.h26 #define HECI_H_CSR_IE REG_BIT(0)
27 #define HECI_H_CSR_IS REG_BIT(1)
28 #define HECI_H_CSR_IG REG_BIT(2)
29 #define HECI_H_CSR_RDY REG_BIT(3)
30 #define HECI_H_CSR_RST REG_BIT(4)
40 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
45 #define HECI1_FWSTS5_HUC_AUTH_DONE REG_BIT(19)
49 #define HECI_H_GS1_ER_PREP REG_BIT(0)
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dsb_regs.h18 #define DSB_ENABLE REG_BIT(31)
19 #define DSB_BUF_REITERATE REG_BIT(29)
20 #define DSB_WAIT_FOR_VBLANK REG_BIT(28)
21 #define DSB_WAIT_FOR_LINE_IN REG_BIT(27)
22 #define DSB_HALT REG_BIT(16)
23 #define DSB_NON_POSTED REG_BIT(8)
24 #define DSB_STATUS_BUSY REG_BIT(0)
26 #define DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31)
32 #define DSB_POLL_ENABLE REG_BIT(31)
40 #define DSB_HP_IDLE_STATUS REG_BIT(31)
[all …]
H A Dintel_psr_regs.h14 #define EXITLINE_ENABLE REG_BIT(31)
28 #define EDP_PSR_ENABLE REG_BIT(31)
29 #define BDW_PSR_SINGLE_FRAME REG_BIT(30)
30 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
31 #define EDP_PSR_LINK_STANDBY REG_BIT(27)
41 #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
42 #define EDP_PSR_TP_MASK REG_BIT(11)
45 #define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */
75 #define TGL_PSR_ERROR REG_BIT(2)
76 #define TGL_PSR_POST_EXIT REG_BIT(1)
[all …]
H A Dintel_hdcp_regs.h15 #define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
16 #define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)
17 #define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
19 #define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
20 #define HDCP_FUSE_ERROR REG_BIT(6)
21 #define HDCP_FUSE_DONE REG_BIT(5)
22 #define HDCP_KEY_LOAD_STATUS REG_BIT(1)
23 #define HDCP_KEY_LOAD_DONE REG_BIT(0)
29 #define HDCP_TRANSA_REP_PRESENT REG_BIT(31)
30 #define HDCP_TRANSB_REP_PRESENT REG_BIT(30)
[all …]
H A Dintel_dvo_regs.h15 #define DVO_ENABLE REG_BIT(31)
16 #define DVO_PIPE_SEL_MASK REG_BIT(30)
22 #define DVO_INTERRUPT_SELECT REG_BIT(27)
23 #define DVO_DEDICATED_INT_ENABLE REG_BIT(26)
25 #define DVO_USE_VGA_SYNC REG_BIT(15)
26 #define DVO_DATA_ORDER_MASK REG_BIT(14)
29 #define DVO_VSYNC_DISABLE REG_BIT(11)
30 #define DVO_HSYNC_DISABLE REG_BIT(10)
31 #define DVO_VSYNC_TRISTATE REG_BIT(9)
32 #define DVO_HSYNC_TRISTATE REG_BIT(8)
[all …]
H A Dintel_vga_regs.h14 #define VGA_DISP_DISABLE REG_BIT(31)
15 #define VGA_2X_MODE REG_BIT(30) /* pre-ilk */
16 #define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */
20 #define VGA_BORDER_ENABLE REG_BIT(26)
21 #define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
23 #define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */
24 #define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */
25 #define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */
26 #define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20)
27 #define VGA_PALETTE_BYPASS REG_BIT(19)
[all …]
H A Dintel_dp_aux_regs.h46 #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
47 #define DP_AUX_CH_CTL_DONE REG_BIT(30)
48 #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
49 #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
55 #define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
60 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */
61 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */
62 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
63 #define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */
64 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */
[all …]
H A Dvlv_dpio_phy_regs.h41 #define DPIO_ENABLE_CALIBRATION REG_BIT(11)
48 #define DPIO_REFSEL_OVERRIDE REG_BIT(27)
75 #define DPIO_PCS_TX_LANE2_RESET REG_BIT(16)
76 #define DPIO_PCS_TX_LANE1_RESET REG_BIT(7)
77 #define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4)
78 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3)
83 #define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23)
84 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22)
85 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21)
90 #define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5)
[all …]
H A Dintel_crt_regs.h14 #define ADPA_DAC_ENABLE REG_BIT(31)
15 #define ADPA_PIPE_SEL_MASK REG_BIT(30)
23 #define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23)
24 #define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22)
27 #define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21)
30 #define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20)
38 #define ADPA_CRT_HOTPLUG_VOLREF_MASK REG_BIT(17)
41 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER REG_BIT(16)
42 #define ADPA_USE_VGA_HVPOLARITY REG_BIT(15)
43 #define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11)
[all …]
H A Dbxt_dpio_phy_regs.h37 #define PORT_PLL_ENABLE REG_BIT(31)
38 #define PORT_PLL_LOCK REG_BIT(30)
39 #define PORT_PLL_REF_SEL REG_BIT(27)
40 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
41 #define PORT_PLL_POWER_STATE REG_BIT(25)
58 #define PORT_PLL_RECALIBRATE REG_BIT(14)
59 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
77 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
92 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
104 #define PHY_POWER_GOOD REG_BIT(16)
[all …]
H A Dintel_sprite_regs.h13 #define DVS_ENABLE REG_BIT(31)
14 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
15 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
21 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
22 #define DVS_SOURCE_KEY REG_BIT(22)
23 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
24 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
30 #define DVS_ROTATE_180 REG_BIT(15)
31 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
32 #define DVS_TILED REG_BIT(10)
[all …]
H A Di9xx_plane_regs.h16 #define DISP_ENABLE REG_BIT(31)
17 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
32 #define DISP_STEREO_ENABLE REG_BIT(25)
33 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
36 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
37 #define DISP_LINE_DOUBLE REG_BIT(20)
38 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
39 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
40 #define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
41 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
[all …]
H A Dintel_combo_phy_regs.h28 #define CL_POWER_DOWN_ENABLE REG_BIT(4)
33 #define PG_SEQ_DELAY_OVERRIDE_ENABLE REG_BIT(24)
43 #define EDP4K2K_MODE_OVRD_EN REG_BIT(3)
44 #define EDP4K2K_MODE_OVRD_OPTIMIZED REG_BIT(2)
47 #define ICL_LANE_ENABLE_AUX REG_BIT(0)
55 #define COMP_INIT REG_BIT(31)
70 #define IREFGEN REG_BIT(24)
91 #define COMMON_KEEPER_EN REG_BIT(26)
110 #define SWING_SEL_UPPER_MASK REG_BIT(15)
122 #define LOADGEN_SELECT REG_BIT(31)
[all …]
H A Dintel_snps_phy_regs.h29 #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
30 #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
31 #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
35 #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
36 #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
37 #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
39 #define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
42 #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
43 #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
51 #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
[all …]
H A Dskl_universal_plane_regs.h38 #define PLANE_CTL_ENABLE REG_BIT(31)
41 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
42 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
67 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
71 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
72 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
73 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
79 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
80 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
81 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
[all …]
H A Dintel_audio_regs.h12 #define G4X_ELD_VALID REG_BIT(14)
15 #define G4X_ELD_ACK REG_BIT(4)
28 #define IBX_ELD_ACK REG_BIT(4)
30 #define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
58 #define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29)
59 #define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28)
81 #define AUD_CONFIG_DISABLE_NCTS REG_BIT(3)
94 #define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21)
95 #define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20)
[all …]
H A Dintel_cursor_regs.h14 #define CURSOR_ENABLE REG_BIT(31)
15 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
29 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
30 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
31 #define MCURSOR_ROTATE_180 REG_BIT(15)
32 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
48 #define CURSOR_POS_Y_SIGN REG_BIT(31)
51 #define CURSOR_POS_X_SIGN REG_BIT(15)
67 #define CUR_FBC_EN REG_BIT(31)
81 #define CUR_WM_EN REG_BIT(31)
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_reg.h120 #define DEPRESENT REG_BIT(9)
123 #define LMEM_INIT REG_BIT(7)
124 #define DRIVERFLR REG_BIT(31)
126 #define DRIVERFLR_STATUS REG_BIT(31)
282 #define HECI_H_CSR_IE REG_BIT(0)
283 #define HECI_H_CSR_IS REG_BIT(1)
284 #define HECI_H_CSR_IG REG_BIT(2)
285 #define HECI_H_CSR_RDY REG_BIT(3)
286 #define HECI_H_CSR_RST REG_BIT(4)
289 #define HECI_H_GS1_ER_PREP REG_BIT(0)
[all …]
H A Di915_perf_oa_regs.h147 #define GEN12_OAM_BUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
151 #define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE REG_BIT(1)
152 #define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME REG_BIT(0)
156 #define GEN12_OAM_CONTROL_COUNTER_ENABLE REG_BIT(0)
159 #define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT REG_BIT(12)
160 #define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6)
161 #define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5)
162 #define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS REG_BIT(2)
163 #define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1)
166 #define GEN12_OAM_STATUS_COUNTER_OVERFLOW REG_BIT(2)
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h38 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3)
75 #define GEN11_MCR_MULTICAST REG_BIT(31)
165 #define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
173 #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
176 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
178 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
242 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
328 #define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */
331 #define RING_FAULT_VALID REG_BIT(0)
356 #define AUX_INV REG_BIT(0)
[all …]
H A Dintel_engine_regs.h48 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
49 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
50 #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
51 #define GEN6_BSD_GO_INDICATOR REG_BIT(4)
52 #define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
53 #define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
54 #define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
74 #define ASYNC_FLIP_PERF_DISABLE REG_BIT(14)
75 #define MI_FLUSH_ENABLE REG_BIT(12)
76 #define TGL_NESTED_BB_EN REG_BIT(12)
[all …]
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_mi_commands.h29 #define MI_ARB_ENABLE REG_BIT(0)
38 #define MI_SDI_GGTT REG_BIT(22)
42 REG_BIT(21))
45 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
46 #define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
48 #define MI_LRI_FORCE_POSTED REG_BIT(12)
52 #define MI_SRM_USE_GGTT REG_BIT(22)
53 #define MI_SRM_ADD_CS_OFFSET REG_BIT(19)
56 #define MI_FLUSH_DW_PROTECTED_MEM_EN REG_BIT(22)
57 #define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
[all …]
/linux/drivers/gpu/drm/xe/tests/
H A Dxe_rtp_test.c67 .expected_set_bits = REG_BIT(0) | REG_BIT(1),
68 .expected_clr_bits = REG_BIT(0) | REG_BIT(1),
75 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
79 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
87 .expected_set_bits = REG_BIT(0),
88 .expected_clr_bits = REG_BIT(0),
95 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
99 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
107 .expected_set_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
108 .expected_clr_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
[all …]

123