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Searched refs:GICR_CTLR_ENABLE_LPIS (Results 1 – 5 of 5) sorted by relevance

/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c269 return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS; in vgic_lpis_enabled()
295 if (!(val & GICR_CTLR_ENABLE_LPIS)) { in vgic_mmio_write_v3r_ctlr()
301 GICR_CTLR_ENABLE_LPIS, in vgic_mmio_write_v3r_ctlr()
303 if (ctlr != GICR_CTLR_ENABLE_LPIS) in vgic_mmio_write_v3r_ctlr()
311 GICR_CTLR_ENABLE_LPIS); in vgic_mmio_write_v3r_ctlr()
/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3.c447 ctlr |= GICR_CTLR_ENABLE_LPIS; in gic_rdist_enable_lpis()
/linux/tools/testing/selftests/kvm/include/arm64/
H A Dgic_v3.h129 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) macro
/linux/include/linux/irqchip/
H A Darm-gic-v3.h129 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) macro
/linux/drivers/irqchip/
H A Dirq-gic-v3-its.c3083 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) { in allocate_lpi_tables()
3165 (val & GICR_CTLR_ENABLE_LPIS)) { in its_cpu_init_lpis()
3239 val |= GICR_CTLR_ENABLE_LPIS; in its_cpu_init_lpis()
5366 if (!(val & GICR_CTLR_ENABLE_LPIS)) in redist_disable_lpis()
5388 val &= ~GICR_CTLR_ENABLE_LPIS; in redist_disable_lpis()
5414 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { in redist_disable_lpis()