| /kvm-unit-tests/x86/ |
| H A D | hyperv_clock.c | 29 static u64 hvclock_tsc_to_ticks(struct hv_reference_tsc_page *shadow, uint64_t tsc) in hvclock_tsc_to_ticks() argument
31 u64 delta = tsc; in hvclock_tsc_to_ticks()
100 printf("warp on CPU %d, TSC page value = %ld prev TSC page value = %ld!\n", i, in hv_clock_test()
130 report(pass, "TSC reference precision test"); in check_test()
190 report_abort("Reference TSC page not available\n"); in main()
197 printf("refcnt %" PRId64", TSC %" PRIx64", TSC reference %" PRId64"\n", in main()
206 printf("refcnt %" PRId64" (delta %" PRId64"), TSC %" PRIx64", " in main()
207 "TSC reference %" PRId64" (delta %" PRId64")\n", in main()
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| H A D | README | 36 tsc: write to tsc(0) and write to tsc(100000000000) and read it back
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| H A D | tsc_adjust.c | 22 "TSC adjustment for MSR_IA32_TSC_ADJUST value"); in main()
32 report(t1 <= t4 - t5, "Internal TSC advances across write to IA32_TSC"); in main()
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| H A D | unittests.cfg | 13 qemu_params = -cpu qemu64,+x2apic,+tsc-deadline -machine kernel_irqchip=split
26 qemu_params = -cpu qemu64,+x2apic,+tsc-deadline
36 qemu_params = -cpu qemu64,-x2apic,+tsc-deadline -machine pit=off
109 qemu_params = -cpu qemu64,+x2apic,+tsc-deadline
115 qemu_params = -cpu qemu64,+x2apic,+tsc-deadline
243 [tsc]
244 file = tsc.flat
498 check = /sys/devices/system/clocksource/clocksource0/current_clocksource=tsc
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| H A D | tscdeadline_latency.c | 16 * # echo x86-tsc > trace_clock
96 printf("tsc deadline timer enabled\n"); in test_tsc_deadline_timer()
98 printf("tsc deadline timer not detected, aborting\n"); in test_tsc_deadline_timer()
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| H A D | kvmclock_test.c | 100 printf("TSC cycles: %lld\n", end - begin); in cycle_test()
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| H A D | apic.c | 59 report(tdt_count == 1, "tsc deadline timer"); in __test_tsc_deadline_timer()
60 report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing"); in __test_tsc_deadline_timer()
81 report_skip("tsc deadline timer not detected"); in test_tsc_deadline_timer()
502 * as TSC), however QEMU seems to be using nanosecond. In all in test_apic_timer_one_shot()
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| H A D | pmu.c | 891 * core crystal clock, TSC, or bus clock. Calibrate to the TSC
919 * On a 2.6GHz Ice Lake, with the TSC frequency at 104 times in set_ref_cycle_expectations()
921 * TSC : ref cycles ratio of around 105 with ECX initialized in set_ref_cycle_expectations()
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| H A D | Makefile.common | 79 tests-common = $(TEST_DIR)/vmexit.$(exe) $(TEST_DIR)/tsc.$(exe) \
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| H A D | svm.h | 55 VMCB_CLEAN_INTERCEPTS = 1, /* Intercept vectors, TSC offset, pause filter count */
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| H A D | pmu_pebs.c | 40 u64 tsc; member
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| H A D | vmx_tests.c | 8854 * list, the value saved is not subject to the TSC offset that is
8863 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__); in vmx_store_tsc_test()
9129 * the TSC changes due to a TSC increment (where X is
9134 * The guest code above reads the starting TSC after VM-entry. At this
9136 * the guest code reads the current TSC in a loop, storing the value
9143 * must be delivered before the next instruction retires. Hence, a TSC
9145 * cannot be stored. If a TSC value past the deadline *is* stored,
9181 "Last stored guest TSC (%lu) < TSC deadline (%lu)", in vmx_preemption_timer_expiry_test()
10323 * Set 'use TSC offsetting' and set the guest offset to the
10324 * inverse of the host's current TSC value, so that the guest starts running
[all …]
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| H A D | svm_tests.c | 746 /* number of bits to shift tsc right for stable result */
776 report(duration == actual_duration, "tsc delay (expected: %lu, actual: %lu)", in svm_tsc_scale_run_testcase()
785 report_skip("TSC scale not supported in the guest"); in svm_tsc_scale_test()
790 "initial TSC scale ratio"); in svm_tsc_scale_test()
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| /kvm-unit-tests/ci/ |
| H A D | cirrus-ci-macos-i386.yml | 25 tsc
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| H A D | cirrus-ci-macos-x86-64.yml | 29 tsc
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| H A D | cirrus-ci-fedora.yml | 51 tsc
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| /kvm-unit-tests/ |
| H A D | .gitlab-ci.yml | 327 tsc
361 tsc
398 tsc
445 tsc
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| /kvm-unit-tests/lib/x86/ |
| H A D | processor.h | 823 unsigned long long tsc; in fenced_rdtsc() local
829 tsc = eax | ((unsigned long long)edx << 32); in fenced_rdtsc()
831 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); in fenced_rdtsc()
833 return tsc; in fenced_rdtsc()
851 static inline void wrtsc(u64 tsc) in wrtsc() argument
853 wrmsr(MSR_IA32_TSC, tsc); in wrtsc()
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| H A D | msr.h | 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
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