| /qemu/target/arm/tcg/ |
| H A D | mte_helper.h | 38 * accessible, and do not take watchpoint traps. The calling code must
39 * handle those cases in the right priority compared to MTE traps.
41 * that the page is going to be accessible. We will take watchpoint traps.
43 * traps and watchpoint traps.
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| H A D | op_helper.c | 57 * SIMD/FP access traps, which are reported as uncategorized in raise_exception()
796 * HSTR_EL2 traps from EL1 are checked earlier, in generated code; in HELPER()
797 * we only need to check here for traps from EL0. in HELPER()
818 * Fine-grained traps also are lower priority than undef-to-EL1, in HELPER()
820 * order with other EL2 traps because the syndrome value is the same. in HELPER()
863 /* CP_ACCESS_TRAP* traps are always direct to a specified EL */ in HELPER()
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| H A D | translate.h | 98 * information from traps due to FP being disabled, we can't do a single
145 /* True if fine-grained traps are active */
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| H A D | tlb-insns.c | 17 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
27 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
38 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
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| /qemu/linux-user/sh4/ |
| H A D | cpu_loop.c | 74 /* Most of the traps imply an exception or interrupt, which in cpu_loop()
77 a few exceptions for traps internal to QEMU. */ in cpu_loop()
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| /qemu/libdecnumber/ |
| H A D | decContext.c | 97 context->traps=DEC_Errors; /* all but informational */ in decContextDefault()
112 context->traps=0; /* no traps set */ in decContextDefault()
123 context->traps=0; /* no traps set */ in decContextDefault()
134 context->traps=0; /* no traps set */ in decContextDefault()
241 if (status & context->traps) raise(SIGFPE); in decContextSetStatus()
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| /qemu/linux-user/alpha/ |
| H A D | cpu_loop.c | 165 /* Most of the traps imply a transition through PALcode, which in cpu_loop()
168 few exceptions for traps internal to QEMU. */ in cpu_loop()
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| /qemu/tests/tcg/riscv64/ |
| H A D | issue1060.S | 21 # When an instruction traps, compare it to the insn in memory.
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| /qemu/include/libdecnumber/ |
| H A D | decContext.h | 48 /* traps -- only defined bits may be set */
85 uint32_t traps; /* trap-enabler flags */ member
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| /qemu/target/riscv/ |
| H A D | cpu_helper.c | 852 * external trap. See 6.1.2. External Traps, table 8 External Trap Enable in riscv_ctr_check_xte()
887 * Special cases for traps and trap returns:
889 * 1- Traps, and trap returns, between enabled modes are recorded as normal.
890 * 2- Traps from an inhibited mode to an enabled mode, and trap returns from an
892 * cases, the PC from the inhibited mode (source PC for traps, and target PC
896 * Traps from an enabled mode to an inhibited mode, known as external traps,
898 * By default external traps are not recorded, but a handshake mechanism exists
900 * can opt-in to allowing CTR to record traps into that mode even when the mode
965 /* Case 2 for traps. */ in riscv_ctr_add_entry()
2148 * Handle Traps
[all …]
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| /qemu/docs/devel/ |
| H A D | uefi-vars.rst | 33 configures the shared buffer location and size, and traps to the host
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| /qemu/linux-user/ppc/ |
| H A D | cpu_loop.c | 370 /* Most of the traps imply a transition through kernel mode, in cpu_loop()
373 * are a few exceptions for traps internal to QEMU. in cpu_loop()
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| /qemu/include/hw/xen/interface/arch-x86/ |
| H A D | xen.h | 116 * ` HYPERVISOR_set_trap_table(const struct trap_info traps[]);
121 * Terminate the array with a sentinel entry, with traps[].address==0.
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| /qemu/target/arm/ |
| H A D | debug_helper.c | 787 * Check for traps to "powerdown debug" registers, which are controlled
808 * Check for traps to "debug ROM" registers, which are controlled
829 * Check for traps to general debug registers, which are controlled
852 /* MCDR_EL3.TDMA doesn't apply for FEAT_NV traps */ in access_dbgvcr32()
860 * Check for traps to Debug Comms Channel registers. If FEAT_FGT
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| H A D | syndrome.h | 112 * The exception is FP/SIMD access traps -- these report extra information
|
| H A D | internals.h | 1892 * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps in arm_fgt_active()
1894 * traps on registers that are only accessible at EL1 because if the test in arm_fgt_active()
1896 * FGT traps only happen when EL2 is enabled and EL1 is AArch64; in arm_fgt_active()
1897 * traps from AArch32 only happen for the EL0 is AArch32 case. in arm_fgt_active()
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| /qemu/target/tricore/ |
| H A D | cpu.h | 168 /* TriCore Traps Classes*/
|
| /qemu/libdecnumber/dpd/ |
| H A D | decimal32.c | 101 decContextDefault(&dc, DEC_INIT_DECIMAL32); /* [no traps] */ in decimal32FromNumber()
386 /* (setting of status and traps) and for the rounding mode, only. */
394 decContextDefault(&dc, DEC_INIT_DECIMAL32); /* no traps, please */ in decimal32FromString()
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| H A D | decimal128.c | 105 decContextDefault(&dc, DEC_INIT_DECIMAL128); /* [no traps] */ in decimal128FromNumber()
457 /* (setting of status and traps) and for the rounding mode, only. */
465 decContextDefault(&dc, DEC_INIT_DECIMAL128); /* no traps, please */ in decimal128FromString()
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| /qemu/target/s390x/tcg/ |
| H A D | vec_fpu_helper.c | 46 /* Check for traps and construct the VXC */ in check_ieee_exc()
59 /* inexact has lowest priority on traps */ in check_ieee_exc()
70 /* on traps, the fpc flags are not updated, instruction is suppressed */ in handle_ieee_exc()
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| H A D | fpu_helper.c | 90 * 2. Only traps due to invalid/divbyzero are suppressing. Other traps in handle_exceptions()
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| /qemu/target/avr/ |
| H A D | helper.c | 202 * in case the load operation traps.
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| /qemu/linux-user/mips/ |
| H A D | cpu_loop.c | 187 * handling code in arch/mips/kernel/traps.c. in cpu_loop()
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| /qemu/linux-user/sparc/ |
| H A D | cpu_loop.c | 204 /* Avoid ifdefs below for the v9 and pre-v9 hw traps. */
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| /qemu/target/hppa/ |
| H A D | cpu.h | 63 /* Hardware exceptions, interrupts, faults, and traps. */
|