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/linux/drivers/clocksource/
H A Dtimer-ti-dm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * linux/arch/arm/plat-omap/dmtimer.c
5 * OMAP Dual-Mode Timers
7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
22 #include <linux/clk-provider.h>
31 #include <linux/platform_data/dmtimer-omap.h>
33 #include <clocksource/timer-ti-dm.h>
36 * timer errata flags
40 * timer counter register is never read. For more details please refer to
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H A Dtimer-zevio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/clocksource/zevio-timer.c
64 struct zevio_timer *timer = container_of(dev, struct zevio_timer, in zevio_timer_set_event() local
67 writel(delta, timer->timer1 + IO_CURRENT_VAL); in zevio_timer_set_event()
69 timer->timer1 + IO_CONTROL); in zevio_timer_set_event()
76 struct zevio_timer *timer = container_of(dev, struct zevio_timer, in zevio_timer_shutdown() local
79 /* Disable timer interrupts */ in zevio_timer_shutdown()
80 writel(0, timer->interrupt_regs + IO_INTR_MSK); in zevio_timer_shutdown()
81 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_shutdown()
82 /* Stop timer */ in zevio_timer_shutdown()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 bool "BCM2835 timer driver" if COMPILE_TEST
39 Enables the support for the BCM2835 timer driver.
42 bool "BCM mobile timer driver" if COMPILE_TEST
45 Enables the support for the BCM Kona mobile timer driver.
48 bool "Texas Instruments DaVinci timer driver" if COMPILE_TEST
50 Enables the support for the TI DaVinci timer driver.
53 bool "Digicolor timer driver" if COMPILE_TEST
57 Enables the support for the digicolor timer driver.
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_TIMER_OF) += timer-of.o
3 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
4 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
5 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
6 obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
7 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
8 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
9 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
10 obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
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H A Dtimer-microchip-pit64b.c1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
38 #define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
40 #define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
51 * struct mchp_pit64b_timer - PIT64B timer data structure
65 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
66 * @timer: PIT64B timer
70 struct mchp_pit64b_timer timer; member
79 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
80 * @timer: PIT64B timer
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H A Dtimer-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip timer support
44 struct rk_timer timer; member
52 return &container_of(ce, struct rk_clkevt, ce)->timer; in rk_timer()
55 static inline void rk_timer_disable(struct rk_timer *timer) in rk_timer_disable() argument
57 writel_relaxed(TIMER_DISABLE, timer->ctrl); in rk_timer_disable()
60 static inline void rk_timer_enable(struct rk_timer *timer, u32 flags) in rk_timer_enable() argument
62 writel_relaxed(TIMER_ENABLE | flags, timer->ctrl); in rk_timer_enable()
66 struct rk_timer *timer) in rk_timer_update_counter() argument
68 writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); in rk_timer_update_counter()
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H A Ddw_apb_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
49 static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs) in apbt_readl() argument
51 return readl(timer->base + offs); in apbt_readl()
54 static inline void apbt_writel(struct dw_apb_timer *timer, u32 val, in apbt_writel() argument
57 writel(val, timer->base + offs); in apbt_writel()
60 static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs) in apbt_readl_relaxed() argument
62 return readl_relaxed(timer->base + offs); in apbt_readl_relaxed()
65 static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val, in apbt_writel_relaxed() argument
68 writel_relaxed(val, timer->base + offs); in apbt_writel_relaxed()
71 static void apbt_eoi(struct dw_apb_timer *timer) in apbt_eoi() argument
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/linux/drivers/rtc/
H A Drtc-brcmstb-waketimer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2014-2023 Broadcom
48 static inline bool brcmstb_waketmr_is_pending(struct brcmstb_waketmr *timer) in brcmstb_waketmr_is_pending() argument
52 reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT); in brcmstb_waketmr_is_pending()
56 static inline void brcmstb_waketmr_clear_alarm(struct brcmstb_waketmr *timer) in brcmstb_waketmr_clear_alarm() argument
60 if (timer->alarm_en && timer->alarm_irq) in brcmstb_waketmr_clear_alarm()
61 disable_irq(timer->alarm_irq); in brcmstb_waketmr_clear_alarm()
62 timer->alarm_en = false; in brcmstb_waketmr_clear_alarm()
63 reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER); in brcmstb_waketmr_clear_alarm()
64 writel_relaxed(reg - 1, timer->base + BRCMSTB_WKTMR_ALARM); in brcmstb_waketmr_clear_alarm()
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/linux/include/linux/
H A Dhrtimer.h1 // SPDX-License-Identifier: GPL-2.0
3 * hrtimers - High-resolution kernel timers
19 #include <linux/percpu-defs.h>
21 #include <linux/timer.h>
26 * HRTIMER_MODE_ABS - Time value is absolute
27 * HRTIMER_MODE_REL - Time value is relative to now
28 * HRTIMER_MODE_PINNED - Timer is bound to CPU (is only considered
29 * when starting the timer)
30 * HRTIMER_MODE_SOFT - Timer callback function will be executed in
32 * HRTIMER_MODE_HARD - Timer callback function will be executed in
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/linux/net/netfilter/
H A Dxt_IDLETIMER.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Netfilter module to trigger a timer when packet matches.
6 * After timer expires a kevent will be sent.
9 * Written by Timo Teras <ext-timo.teras@nokia.com>
20 #include <linux/timer.h>
35 struct timer_list timer; member
56 if (!strcmp(label, entry->attr.attr.name)) in __idletimer_tg_find_by_label()
66 struct idletimer_tg *timer; in idletimer_tg_show() local
73 timer = __idletimer_tg_find_by_label(attr->attr.name); in idletimer_tg_show()
74 if (timer) { in idletimer_tg_show()
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/linux/tools/testing/selftests/kvm/arm64/
H A Darch_timer_edge_cases.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch_timer_edge_cases.c - Tests the aarch64 timer IRQ functionality.
5 * The test validates some edge cases related to the arch-timer:
6 * - timers above the max TVAL value.
7 * - timers in the past
8 * - moving counters ahead and behind pending timers.
9 * - reprograming timers.
10 * - timers fired multiple times.
11 * - masking/unmasking using the timer control mask.
27 /* tval is a signed 32-bit int. */
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/linux/Documentation/devicetree/bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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H A Dmediatek,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
14 CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer)
15 and SYST (System Timer).
20 - items:
21 - enum:
22 - mediatek,mt6577-timer
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H A Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
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H A Drockchip,rk-timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Timer
10 - Daniel Lezcano <daniel.lezcano@linaro.org>
15 - const: rockchip,rk3288-timer
16 - const: rockchip,rk3399-timer
17 - items:
18 - enum:
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/linux/sound/isa/gus/
H A Dgus_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Routines for Gravis UltraSound soundcards - Timers
14 * Timer 1 - 80us
17 static int snd_gf1_timer1_start(struct snd_timer * timer) in snd_gf1_timer1_start() argument
24 gus = snd_timer_chip(timer); in snd_gf1_timer1_start()
25 spin_lock_irqsave(&gus->reg_lock, flags); in snd_gf1_timer1_start()
26 ticks = timer->sticks; in snd_gf1_timer1_start()
27 tmp = (gus->gf1.timer_enabled |= 4); in snd_gf1_timer1_start()
28 snd_gf1_write8(gus, SNDRV_GF1_GB_ADLIB_TIMER_1, 256 - ticks); /* timer 1 count */ in snd_gf1_timer1_start()
29 snd_gf1_write8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL, tmp); /* enable timer 1 IRQ */ in snd_gf1_timer1_start()
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/linux/sound/core/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <sound/timer.h>
39 MODULE_DESCRIPTION("ALSA timer interface");
47 MODULE_ALIAS("devname:snd/timer");
93 s32 tstamp_sec; /* Timestamp - last update */
105 s64 tstamp_sec; /* Timestamp - last update */
116 /* Internal data structure for keeping the state of the userspace-driven timer */
119 struct snd_timer *timer; member
140 static int snd_timer_free(struct snd_timer *timer);
145 static void snd_timer_reschedule(struct snd_timer * timer, unsigned long ticks_left);
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/linux/arch/s390/kernel/
H A Dvtime.c1 // SPDX-License-Identifier: GPL-2.0
3 * Virtual cpu timer based timer functions.
39 u64 timer; in set_vtimer() local
42 " stpt %0\n" /* Store current cpu timer value */ in set_vtimer()
44 : "=Q" (timer) : "Q" (expires)); in set_vtimer()
45 lc->system_timer += lc->last_update_timer - timer; in set_vtimer()
46 lc->last_update_timer = expires; in set_vtimer()
70 delta = cycles_new[i] - cycles_old[i]; in update_mt_scaling()
91 delta = new - *tsk_vtime; in update_tsk_timer()
110 p->stimescaled += cputime_to_nsecs(scale_vtime(cputime)); in account_system_index_scaled()
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/linux/arch/nios2/kernel/
H A Dtime.c2 * Copyright (C) 2013-2014 Altera Corporation
22 #define ALTR_TIMER_COMPATIBLE "altr,timer-1.0"
42 struct nios2_timer timer; member
47 struct nios2_timer timer; member
63 static u16 timer_readw(struct nios2_timer *timer, u32 offs) in timer_readw() argument
65 return readw(timer->base + offs); in timer_readw()
68 static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs) in timer_writew() argument
70 writew(val, timer->base + offs); in timer_writew()
73 static inline unsigned long read_timersnapshot(struct nios2_timer *timer) in read_timersnapshot() argument
77 timer_writew(timer, 0, ALTERA_TIMER_SNAPL_REG); in read_timersnapshot()
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/linux/kernel/time/
H A Dhrtimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
4 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
5 * Copyright(C) 2006-2007 Timesys Corp., Thomas Gleixner
7 * High-resolution kernel timers
9 * In contrast to the low-resolution timeout API, aka timer wheel,
16 * Based on the original timer wheel code
42 #include <linux/timer.h>
48 #include <trace/events/timer.h>
50 #include "tick-internal.h"
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H A Dposix-cpu-timers.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/posix-timers.h>
13 #include <trace/events/timer.h>
20 #include "posix-timers.h"
22 static void posix_cpu_timer_rearm(struct k_itimer *timer);
28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
29 pct->timers_active = true; in posix_cputimers_group_init()
34 * Called after updating RLIMIT_CPU to run cpu timer and update
35 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if
39 * Returns 0 on success, -ESRCH on failure. Can fail if the task is exiting and
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/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
13 #define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
16 /* 16-bit shared register offset macros */
17 #define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
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/linux/sound/core/seq/oss/
H A Dseq_oss_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Timer control routines
24 static void calc_alsa_tempo(struct seq_oss_timer *timer);
29 * create and register a new timer.
41 rec->dp = dp; in snd_seq_oss_timer_new()
42 rec->cur_tick = 0; in snd_seq_oss_timer_new()
43 rec->realtime = 0; in snd_seq_oss_timer_new()
44 rec->running = 0; in snd_seq_oss_timer_new()
45 rec->oss_tempo = 60; in snd_seq_oss_timer_new()
46 rec->oss_timebase = 100; in snd_seq_oss_timer_new()
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/linux/tools/testing/selftests/kvm/include/arm64/
H A Darch_timer.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ARM Generic Timer specific interface
34 static inline uint64_t timer_get_cntct(enum arch_timer timer) in timer_get_cntct() argument
38 switch (timer) { in timer_get_cntct()
44 GUEST_FAIL("Unexpected timer type = %u", timer); in timer_get_cntct()
51 static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) in timer_set_cval() argument
53 switch (timer) { in timer_set_cval()
61 GUEST_FAIL("Unexpected timer type = %u", timer); in timer_set_cval()
67 static inline uint64_t timer_get_cval(enum arch_timer timer) in timer_get_cval() argument
69 switch (timer) { in timer_get_cval()
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/linux/arch/loongarch/kvm/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
11 * ktime_to_tick() - Scale ktime_t to timer tick value.
18 return div_u64(delta * vcpu->arch.timer_mhz, MNSEC_PER_SEC); in ktime_to_tick()
23 return div_u64(tick * MNSEC_PER_SEC, vcpu->arch.timer_mhz); in tick_to_ns()
27 enum hrtimer_restart kvm_swtimer_wakeup(struct hrtimer *timer) in kvm_swtimer_wakeup() argument
31 vcpu = container_of(timer, struct kvm_vcpu, arch.swtimer); in kvm_swtimer_wakeup()
33 rcuwait_wake_up(&vcpu->wait); in kvm_swtimer_wakeup()
39 * Initialise the timer to the specified frequency, zero it
43 vcpu->arch.timer_mhz = timer_hz >> 20; in kvm_init_timer()
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