| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | memory.json | 3 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
10 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
16 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
23 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
29 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
36 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
42 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 204
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | memory.json | 21 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
28 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
33 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
40 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
45 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
52 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
57 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 3
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | memory.json | 159 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
166 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
172 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
179 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
185 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
192 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
198 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 204
[all...] |
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-tty | 30 sysfs rather than via ioctls.
39 sysfs rather than via ioctls.
48 sysfs rather than via ioctls.
57 sysfs rather than via ioctls.
66 sysfs rather than via ioctls.
75 sysfs rather than via ioctls.
84 sysfs rather than via ioctls.
93 sysfs rather than via ioctls.
105 sysfs rather than via ioctls.
114 sysfs rather than vi
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | memory.json | 143 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
150 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
156 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
163 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
169 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
176 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
182 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 204
[all...] |
| /linux/drivers/gpu/drm/vc4/tests/ |
| H A D | vc4_test_pv_muxing.c | 294 VC4_PV_MUXING_TEST("More than 3 outputs: DSI0, HDMI0, DSI1, TXP",
299 VC4_PV_MUXING_TEST("More than 3 outputs: DSI0, VEC, DSI1, TXP",
304 VC4_PV_MUXING_TEST("More than 3 outputs: DPI, HDMI0, DSI1, TXP",
309 VC4_PV_MUXING_TEST("More than 3 outputs: DPI, VEC, DSI1, TXP",
489 VC5_PV_MUXING_TEST("More than 3 outputs: DPI, VEC, TXP, DSI1",
494 VC5_PV_MUXING_TEST("More than 3 outputs: DPI, VEC, TXP, HDMI0",
499 VC5_PV_MUXING_TEST("More than 3 outputs: DPI, VEC, TXP, HDMI1",
504 VC5_PV_MUXING_TEST("More than 3 outputs: DPI, VEC, DSI1, HDMI0",
509 VC5_PV_MUXING_TEST("More than 3 outputs: DPI, VEC, DSI1, HDMI1",
514 VC5_PV_MUXING_TEST("More than
[all...] |
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | memory.json | 53 "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
54 "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
59 "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
60 "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load"
84 "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
89 "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
90 "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load"
119 "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
120 "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
125 "BriefDescription": "Final Pump Scope (Group) ended up larger than Initia
[all...] |
| /linux/drivers/net/can/dev/ |
| H A D | bittiming.c | 22 NL_SET_ERR_MSG_FMT(extack, "sjw: %u greater than max sjw: %u", in can_sjw_check()
29 "sjw: %u greater than phase-seg1: %u", in can_sjw_check()
36 "sjw: %u greater than phase-seg2: %u", in can_sjw_check()
59 NL_SET_ERR_MSG_FMT(extack, "prop-seg + phase-seg1: %u less than tseg1-min: %u", in can_fixup_bittiming()
64 NL_SET_ERR_MSG_FMT(extack, "prop-seg + phase-seg1: %u greater than tseg1-max: %u", in can_fixup_bittiming()
69 NL_SET_ERR_MSG_FMT(extack, "phase-seg2: %u less than tseg2-min: %u", in can_fixup_bittiming()
74 NL_SET_ERR_MSG_FMT(extack, "phase-seg2: %u greater than tseg2-max: %u", in can_fixup_bittiming()
95 NL_SET_ERR_MSG_FMT(extack, "resulting brp: %u less than brp-min: %u", in can_fixup_bittiming()
100 NL_SET_ERR_MSG_FMT(extack, "resulting brp: %u greater than brp-max: %u", in can_fixup_bittiming()
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ |
| H A D | tlb.json | 28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations."
44 "PublicDescription": "Counts number of memory accesses triggered by a data translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers."
48 "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD."
52 "PublicDescription": "Counts number of memory accesses triggered by a demand data translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers."
56 "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD."
60 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_BLOCK is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
64 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. In this family, this is equal to ITLB_WALK_BLOCK event. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations."
68 "PublicDescription": "Counts number of data translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_PAGE event is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
72 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than
[all...] |
| /linux/Documentation/filesystems/ |
| H A D | inotify.rst | 33 An fd-per-watch quickly consumes more file descriptors than are allowed,
34 more fd's than are feasible to manage, and more fd's than are optimally
37 A watch consumes less memory than an open file, separating the number
72 Additionally, it _is_ possible to more than one instance and
73 juggle more than one queue and thus more than one associated fd. There
75 process can easily want more than one queue.
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ |
| H A D | tlb.json | 28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations."
92 "PublicDescription": "Counts number of memory accesses triggered by a data translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers."
96 "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD."
100 "PublicDescription": "Counts number of memory accesses triggered by a demand data translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers."
104 "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD."
108 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_BLOCK is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
112 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. In this family, this is equal to ITLB_WALK_BLOCK event. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations."
116 "PublicDescription": "Counts number of data translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_PAGE event is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
120 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | memory.json | 84 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
91 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
96 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
103 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
108 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
115 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
120 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 3
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | memory.json | 84 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
91 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
96 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
103 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
108 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
115 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
120 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 3
[all...] |
| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_lan_hmc.h | 16 * The sizes of the variables may be larger than needed due to crossing byte
23 u16 cpuid; /* bigger than needed, see above for reason */
27 u16 dbuff; /* bigger than needed, see above for reason */
29 u16 hbuff; /* bigger than needed, see above for reason */
38 u32 rxmax; /* bigger than needed, see above for reason */
43 u16 lrxqthresh; /* bigger than needed, see above for reason */
49 * The sizes of the variables may be larger than needed due to crossing byte
|
| /linux/arch/arm/nwfpe/ |
| H A D | fpa11_cprt.c | 34 /* Hint to GCC that we'd like a jump table rather than a load of CMPs */ in EmulateCPRT()
157 comparison (cheaper than an 80-bit one). */ in PerformComparison()
221 /* test for less than condition */ in PerformComparison()
229 /* test for greater than or equal condition */ in PerformComparison()
247 /* test for less than condition */ in PerformComparison()
255 /* test for greater than or equal condition */ in PerformComparison()
268 /* test for less than condition */ in PerformComparison()
276 /* test for greater than or equal condition */ in PerformComparison()
294 /* test for less than condition */ in PerformComparison()
302 /* test for greater than o in PerformComparison()
[all...] |
| /linux/tools/testing/selftests/net/forwarding/ |
| H A D | tc_tunnel_key.sh | 119 check_err $? "packet smaller than MTU was not tunneled"
123 check_err $? "packet bigger than MTU matched nofrag (nofrag was set)"
125 check_err $? "packet bigger than MTU matched firstfrag (nofrag was set)"
127 check_err $? "packet bigger than MTU matched nofirstfrag (nofrag was set)"
133 check_err $? "packet bigger than MTU matched nofrag (nofrag was unset)"
135 check_err $? "packet bigger than MTU didn't match firstfrag (nofrag was unset) "
137 check_err $? "packet bigger than MTU didn't match nofirstfrag (nofrag was unset) "
|
| /linux/Documentation/networking/ |
| H A D | ipsec.rst | 20 defined in section 3, is not smaller than the size of the original
26 datagram fragmentation when the expanded datagram is larger than the
31 where IP datagrams of size smaller than the threshold are sent in the
37 is smaller than the threshold or the compressed len is larger than original
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | memory.json | 21 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
28 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
33 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
40 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
45 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
52 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
57 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 3
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | memory.json | 62 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
69 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.",
74 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
81 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
86 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
93 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
98 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 25
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | memory.json | 62 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
69 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.",
74 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
81 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
86 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
93 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
98 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 25
[all...] |
| /linux/arch/x86/math-emu/ |
| H A D | README | 74 a value of pi which is accurate to more than 128 bits. As a consequence,
75 the reduced argument is accurate to more than 64 bits for arguments up
76 to a few pi, and accurate to more than 64 bits for most arguments,
96 therefore now fully re-entrant, rather than having just the restricted
103 are fewer than those which applied to the 1.xx series of the emulator.
113 (a) the operands have a higher precision than the current setting of the
116 (c) the magnitude of the exact result (before rounding) is less than 2^-16382.
146 greater than 0xffff appear to be illegal in vm86 mode but are quite
229 than that of an Intel 80486 FPU.
241 arguments greater than p
[all...] |
| H A D | reg_round.S | 49 | smaller than the magnitude of the correct exact result by an amount |
50 | greater than zero and less than one ls bit of the significand. |
53 | less than 0x80000000 <=> the significand is less than 1/2 an ls |
54 | bit smaller than the magnitude of the |
57 | smaller than the magnitude of the true |
59 | greater than 0x80000000 <=> the significand is more than 1/2 an ls |
60 | bit smaller than th
[all...] |
| /linux/Documentation/driver-api/thermal/ |
| H A D | cpu-idle-cooling.rst | 26 budget lower than the requested one and under-utilize the CPU, thus
28 with a power less than the requested power budget and the next OPP
48 belong to the same cluster, with a duration greater than the cluster
132 - It is less than or equal to the latency we tolerate when the
137 - It is greater than the idle state’s target residency we want to go
148 ... which is more than the sustainable power (or there is something
177 Practically, if the running power is less than the targeted power, we
180 running power greater than the targeted power.
192 * The injected idle duration must be greater than the idle state
|
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_tv_regs.h | 39 /* Selects progressive mode rather than interlaced */
247 /* Offset of the start of vsync in field 1, measured in one less than the
253 * Offset of the start of vsync in field 2, measured in one less than the
265 /* Offset of the start of equalization in field 1, measured in one less than
271 * Offset of the start of equalization in field 2, measured in one less than
279 * Offset to start of vertical colorburst, measured in one less than the
285 * Offset to the end of vertical colorburst, measured in one less than the
293 * Offset to start of vertical colorburst, measured in one less than the
299 * Offset to the end of vertical colorburst, measured in one less than the
307 * Offset to start of vertical colorburst, measured in one less than th
[all...] |
| /linux/tools/perf/Documentation/ |
| H A D | perf-ftrace.txt | 89 by using this option more than once. The function argument also
96 argument. Like -T option, this can be used more than once to
111 than once to specify multiple functions. It will be passed to
119 executed from the given function. This can be used more than once to
170 -n/--use-nsec). The setting is ignored if the value results in more than
179 Multiple functions can be given by using this option more than once.
186 can be used more than once to specify multiple functions (or glob
193 can be used more than once to specify multiple functions. It will be
201 can be used more than once to specify multiple functions. It will be
|