| /linux/sound/soc/intel/common/ |
| H A D | soc-acpi-intel-tgl-match.c | 3 * soc-acpi-intel-tgl-match.c - tables and support for TGL ACPI enumeration.
512 .sof_tplg_filename = "sof-tgl-es8336", /* the tplg suffix is added at run time */
523 .sof_tplg_filename = "sof-tgl", /* the tplg suffix is added at run time */
533 .sof_tplg_filename = "sof-tgl-rt1308-ssp2-hdmi-ssp15.tplg"
734 .sof_tplg_filename = "sof-tgl-rt711-rt1308-rt715.tplg",
740 .sof_tplg_filename = "sof-tgl-rt711-rt1308-mono-rt715.tplg",
746 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
752 .sof_tplg_filename = "sof-tgl-rt712.tplg",
758 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
764 .sof_tplg_filename = "sof-tgl-cs42l43-l3-cs35l56-l01.tplg",
[all …]
|
| H A D | Makefile | 8 soc-acpi-intel-tgl-match.o soc-acpi-intel-ehl-match.o \
|
| /linux/sound/soc/sof/intel/ |
| H A D | pci-tgl.c | 36 [SOF_IPC_TYPE_4] = "intel/sof-ipc4/tgl",
39 [SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/tgl",
46 [SOF_IPC_TYPE_3] = "sof-tgl.ri",
47 [SOF_IPC_TYPE_4] = "sof-tgl.ri",
49 .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
69 [SOF_IPC_TYPE_4] = "intel/sof-ipc4/tgl-h",
72 [SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/tgl-h",
79 [SOF_IPC_TYPE_3] = "sof-tgl-h.ri",
80 [SOF_IPC_TYPE_4] = "sof-tgl-h.ri",
82 .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
[all …]
|
| H A D | Makefile | 38 snd-sof-pci-intel-tgl-y := pci-tgl.o tgl.o
48 obj-$(CONFIG_SND_SOC_SOF_INTEL_TGL) += snd-sof-pci-intel-tgl.o
|
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll_mgr.h | 112 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
116 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
124 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
129 * TGL TC PLL 1 port 1 (TC1)
134 * TGL TC PLL 1 port 2 (TC2)
139 * TGL TC PLL 1 port 3 (TC3)
144 * TGL TC PLL 1 port 4 (TC4)
148 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
152 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
214 /* tgl */
|
| H A D | skl_watermark_regs.h | 15 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
17 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
19 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
|
| H A D | skl_universal_plane_regs.h | 81 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
91 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
353 #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
397 /* tgl+ */
413 /* tgl+ */
428 /* tgl+ */
443 /* tgl+ */
|
| H A D | intel_display_regs.h | 857 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
882 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1060 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
1080 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
1088 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
1241 #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
1242 #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl-mtl */
1244 #define GEN12_PIPEDMC_FLIPQ_DONE REG_BIT(24) /* tgl-adl */
1245 #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
1246 #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
[all …]
|
| H A D | intel_vrr.c | 91 * On ICL/TGL VRR hardware inserts one extra scanline in intel_vrr_extra_vblank_delay()
111 /* ICL/TGL hardware imposes flipline>=vmin+1 */ in intel_vrr_flipline_offset()
401 * generate, and on ICL/TGL flipline>=vmin+1, hence we reduce in intel_vrr_compute_config()
466 * TGL: generate VRR "safe window" for DSB vblank waits in intel_vrr_set_transcoder_timings()
|
| H A D | intel_display_limits.h | 105 /* tgl+ */
|
| H A D | intel_psr_regs.h | 62 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
|
| H A D | intel_cursor_regs.h | 107 /* tgl+ */
|
| H A D | intel_dmc.c | 159 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12)
560 /* also disable the flip queue event on the main DMC on TGL */ in disable_dmc_evt()
565 /* also disable the HRR event on the main DMC on TGL/ADLS */ in disable_dmc_evt()
658 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ in need_pipedmc_load_program()
713 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. in can_enable_pipedmc()
|
| /linux/arch/powerpc/platforms/powernv/ |
| H A D | pci-ioda-tce.c | 375 struct iommu_table_group_link *tgl; in pnv_pci_unlink_table_and_group() local
384 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { in pnv_pci_unlink_table_and_group()
385 if (tgl->table_group == table_group) { in pnv_pci_unlink_table_and_group()
386 list_del_rcu(&tgl->next); in pnv_pci_unlink_table_and_group()
387 kfree_rcu(tgl, rcu); in pnv_pci_unlink_table_and_group()
414 struct iommu_table_group_link *tgl = NULL; in pnv_pci_link_table_and_group() local
419 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, in pnv_pci_link_table_and_group()
421 if (!tgl) in pnv_pci_link_table_and_group()
424 tgl->table_group = table_group; in pnv_pci_link_table_and_group()
425 list_add_rcu(&tgl->next, &tbl->it_group_list); in pnv_pci_link_table_and_group()
|
| /linux/drivers/media/rc/img-ir/ |
| H A D | img-ir-rc5.c | 14 unsigned int addr, cmd, tgl, start; in img_ir_rc5_scancode() local
20 tgl = (raw >> 11) & 0x01; in img_ir_rc5_scancode()
34 request->toggle = tgl; in img_ir_rc5_scancode()
|
| /linux/arch/x86/events/intel/ |
| H A D | cstate.c | 55 * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
61 * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
66 * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
72 * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
79 * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
85 * KBL,CML,ICL,TGL,RKL
89 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
94 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL
98 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
|
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_uc_fw.c | 124 fw_def(ALDERLAKE_N, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
126 fw_def(ALDERLAKE_S, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
127 fw_def(ROCKETLAKE, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
128 fw_def(TIGERLAKE, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1))
136 fw_def(ALDERLAKE_P, GT_TYPE_ANY, no_ver(i915, huc, tgl)) \
137 fw_def(ALDERLAKE_S, GT_TYPE_ANY, no_ver(i915, huc, tgl)) \
138 fw_def(ROCKETLAKE, GT_TYPE_ANY, no_ver(i915, huc, tgl)) \
139 fw_def(TIGERLAKE, GT_TYPE_ANY, no_ver(i915, huc, tgl))
|
| /linux/drivers/platform/x86/intel/pmc/ |
| H A D | Makefile | 7 tgl.o adl.o mtl.o arl.o lnl.o ptl.o
|
| /linux/drivers/gpu/drm/imx/dcss/ |
| H A D | dcss-dev.h | 17 #define TGL 0x0C macro
23 #define dcss_toggle(v, c) writel((v), (c) + TGL)
|
| /linux/sound/soc/intel/avs/ |
| H A D | Makefile | 7 snd-soc-avs-y += skl.o apl.o cnl.o icl.o tgl.o mtl.o lnl.o ptl.o
|
| /linux/drivers/gpu/drm/ci/ |
| H A D | test.yml | 313 i915:tgl:
319 GPU_VERSION: tgl
|
| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_tlb.c | 85 /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ in mmio_invalidate_full()
|
| /linux/drivers/gpu/drm/i915/ |
| H A D | intel_device_info.h | 112 /* TGL */
|
| /linux/sound/soc/intel/boards/ |
| H A D | sof_ssp_amp.c | 52 /* BE ID defined in sof-tgl-rt1308-hdmi-ssp.m4 */
|
| /linux/drivers/media/pci/intel/ipu6/ |
| H A D | ipu6-isys-mcd-phy.c | 33 * only 2 phys for TGL U and Y
38 * There are 2 MCD DPHY instances on TGL and 1 MCD DPHY instance on ADL.
110 /* for TGL-U, use 0x80000000 */
|