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/linux-5.10/drivers/slimbus/
Dqcom-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
88 /* Resource group info for manager, and non-ported generic device-components */
103 struct slim_controller ctrl; member
109 struct slim_ctrl_buf rx; member
120 static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf, in qcom_slim_queue_tx() argument
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
131 static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl) in slim_alloc_rxbuf() argument
136 spin_lock_irqsave(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { in slim_alloc_rxbuf()
[all …]
/linux-5.10/drivers/media/radio/wl128x/
Dfmdrv_v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
29 /* -- V4L2 RADIO (/dev/radioX) device file operation interfaces --- */
31 /* Read RX RDS data */
43 return -EIO; in fm_v4l2_fops_read()
46 if (mutex_lock_interruptible(&fmdev->mutex)) in fm_v4l2_fops_read()
47 return -ERESTARTSYS; in fm_v4l2_fops_read()
67 mutex_unlock(&fmdev->mutex); in fm_v4l2_fops_read()
80 rds.text[sizeof(rds.text) - 1] = '\0'; in fm_v4l2_fops_write()
84 return -EFAULT; in fm_v4l2_fops_write()
87 if (mutex_lock_interruptible(&fmdev->mutex)) in fm_v4l2_fops_write()
[all …]
/linux-5.10/drivers/spi/
Dspi-pic32.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
27 u32 ctrl; member
46 #define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
61 #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
75 #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */
88 #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
89 #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
105 u32 speed_hz; /* spi-clk rate */
116 const void *rx; member
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Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
102 void (*rx)(struct spi_imx_data *); member
124 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
129 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
134 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
139 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
145 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
[all …]
/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac5.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
52 { true, "RTES", "RX FSM Timeout Error" },
95 { true, "RXCES", "MTL RX Memory Error" },
96 { true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
97 { true, "RXUES", "MTL RX Memory Error" },
103 { true, "RPCES", "MTL RX Parser Memory Error" },
104 { true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
105 { true, "RPUES", "MTL RX Parser Memory Error" },
191 return -EINVAL; in dwmac5_safety_feat_config()
196 value |= MRXPEE; /* MTL RX Parser ECC */ in dwmac5_safety_feat_config()
[all …]
Ddwxgmac2_core.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
18 void __iomem *ioaddr = hw->pcsr; in dwxgmac2_core_init()
19 u32 tx, rx; in dwxgmac2_core_init() local
22 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_core_init()
25 rx |= XGMAC_CORE_INIT_RX; in dwxgmac2_core_init()
27 if (hw->ps) { in dwxgmac2_core_init()
29 tx &= ~hw->link.speed_mask; in dwxgmac2_core_init()
31 switch (hw->ps) { in dwxgmac2_core_init()
33 tx |= hw->link.xgmii.speed10000; in dwxgmac2_core_init()
36 tx |= hw->link.speed2500; in dwxgmac2_core_init()
[all …]
/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
[all …]
/linux-5.10/sound/soc/fsl/
Dfsl_spdif.c1 // SPDX-License-Identifier: GPL-2.0
26 #include "imx-pcm.h"
84 * struct fsl_spdif_priv - Freescale SPDIF private data
97 * @rxclk: rx clock sources for capture
99 * @sysclk: system clock for rx clock rate measurement
146 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; in fsl_spdif_can_set_clk_rate()
152 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_dpll_lock()
153 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_dpll_lock()
159 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", in spdif_irq_dpll_lock()
162 spdif_priv->dpll_locked = locked ? true : false; in spdif_irq_dpll_lock()
[all …]
/linux-5.10/drivers/net/ethernet/altera/
Daltera_sgdma.c1 // SPDX-License-Identifier: GPL-2.0-only
56 priv->txctrlreg = SGDMA_CTRLREG_ILASTD | in sgdma_initialize()
59 priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP | in sgdma_initialize()
63 INIT_LIST_HEAD(&priv->txlisthd); in sgdma_initialize()
64 INIT_LIST_HEAD(&priv->rxlisthd); in sgdma_initialize()
66 priv->rxdescphys = (dma_addr_t) 0; in sgdma_initialize()
67 priv->txdescphys = (dma_addr_t) 0; in sgdma_initialize()
69 priv->rxdescphys = dma_map_single(priv->device, in sgdma_initialize()
70 (void __force *)priv->rx_dma_desc, in sgdma_initialize()
71 priv->rxdescmem, DMA_BIDIRECTIONAL); in sgdma_initialize()
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/linux-5.10/drivers/media/pci/cobalt/
Dcobalt-irq.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include "cobalt-driver.h"
12 #include "cobalt-irq.h"
13 #include "cobalt-omnitek.h"
17 struct cobalt *cobalt = s->cobalt; in cobalt_dma_stream_queue_handler()
18 int rx = s->video_channel; in cobalt_dma_stream_queue_handler() local
20 COBALT_CVI_FREEWHEEL(s->cobalt, rx); in cobalt_dma_stream_queue_handler()
22 COBALT_CVI_VMR(s->cobalt, rx); in cobalt_dma_stream_queue_handler()
24 COBALT_CVI(s->cobalt, rx); in cobalt_dma_stream_queue_handler()
[all …]
Dcobalt-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Derived from ivtv-ioctl.c and cx18-fileops.c
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include <linux/dma-mapping.h>
15 #include <linux/v4l2-dv-timings.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-event.h>
19 #include <media/v4l2-dv-timings.h>
23 #include "cobalt-alsa.h"
24 #include "cobalt-cpld.h"
[all …]
/linux-5.10/drivers/net/ethernet/intel/igc/
Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
22 u32 ctrl; in igc_reset_hw_base() local
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); in igc_reset_hw_base()
62 * igc_init_nvm_params_base - Init NVM func ptrs.
67 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_base()
74 /* Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_base()
[all …]
Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
25 u32 ctrl; in igc_disable_pcie_master() local
27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; in igc_disable_pcie_master()
29 wr32(IGC_CTRL, ctrl); in igc_disable_pcie_master()
36 timeout--; in igc_disable_pcie_master()
[all …]
/linux-5.10/drivers/atm/
Dhorizon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 Copyright (C) 1995-1999 Madge Networks Ltd.
95 comes with the revision 0 (140-025-01) ASIC.
99 Madge's SAMBA framer or a SUNI-lite device (early versions). It
100 comes with the revision 1 (140-027-01) ASIC.
104 All Horizon-based cards present with the same PCI Vendor and Device
106 to enable bus-mastering (with appropriate latency).
115 up for loop-timing.
122 line-based timing; the internal RAM is zeroed and the allocation of
123 buffers for RX and TX is made; the Burnt In Address is read and
[all …]
/linux-5.10/drivers/tty/serial/
Dapbuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 u32 ctrl; member
29 #define UART_STATUS_OE 0x00000010 /* RX Overrun Error */
30 #define UART_STATUS_PE 0x00000020 /* RX Parity Error */
31 #define UART_STATUS_FE 0x00000040 /* RX Framing Error */
35 * The following defines the bits in the APBUART Ctrl Registers.
46 #define APBBASE(port) ((struct grlib_apbuart_regs_map *)((port)->membase))
48 #define APBBASE_DATA_P(port) (&(APBBASE(port)->data))
49 #define APBBASE_STATUS_P(port) (&(APBBASE(port)->status))
50 #define APBBASE_CTRL_P(port) (&(APBBASE(port)->ctrl))
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/linux-5.10/Documentation/devicetree/bindings/sound/
Dst,stm32-spdifrx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-spdifrx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@st.com>
14 IEC-60958 and IEC-61937.
19 - st,stm32h7-spdifrx
21 "#sound-dai-cells":
30 clock-names:
32 - const: kclk
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/linux-5.10/drivers/net/ethernet/ibm/emac/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Driver for PowerPC 4xx on-chip ethernet controller.
48 #include <asm/dcr-regs.h>
55 * API-correct usage requires additional support state information to be
56 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
65 * controversial, but I really tried to make code API-correct and efficient
66 * at the same time and didn't come up with code I liked :(. --ebs
87 * to avoid re-using the same PHY ID in cases where the arch didn't
92 * probably require in that case to have explicit PHY IDs in the device-tree
103 * if we didn't have completely random interface names at boot too :-) It's
[all …]
/linux-5.10/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
221 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
222 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
[all …]
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
[all …]
/linux-5.10/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
39 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
40 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
88 * e1000_set_phy_type - Set the phy type member in the hw struct.
93 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
94 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
96 switch (hw->phy_id) { in e1000_set_phy_type()
102 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
105 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
[all …]
/linux-5.10/drivers/net/ethernet/netronome/nfp/
Dnfp_net.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
20 #include <linux/io-64-nonatomic-hi-lo.h>
31 if (__nn->dp.netdev) \
32 netdev_printk(lvl, __nn->dp.netdev, fmt, ## args); \
34 dev_printk(lvl, __nn->dp.dev, "ctrl: " fmt, ## args); \
47 if (__dp->netdev) \
48 netdev_warn(__dp->netdev, fmt, ## args); \
50 dev_warn(__dp->dev, fmt, ## args); \
82 #define NFP_NET_MAX_RX_RINGS 64 /* Max. # of Rx rings per device */
[all …]
/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_rule.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
26 return -ENOMEM; in dr_rule_append_to_miss_list()
28 mlx5dr_ste_set_miss_addr(last_ste->hw_ste, in dr_rule_append_to_miss_list()
30 list_add_tail(&new_last_ste->miss_list_node, miss_list); in dr_rule_append_to_miss_list()
33 0, last_ste->hw_ste, in dr_rule_append_to_miss_list()
44 struct mlx5dr_domain *dmn = matcher->tbl->dmn; in dr_rule_create_collision_htbl()
49 new_htbl = mlx5dr_ste_htbl_alloc(dmn->ste_icm_pool, in dr_rule_create_collision_htbl()
59 ste = new_htbl->ste_arr; in dr_rule_create_collision_htbl()
60 mlx5dr_ste_set_miss_addr(hw_ste, nic_matcher->e_anchor->chunk->icm_addr); in dr_rule_create_collision_htbl()
76 mlx5dr_dbg(matcher->tbl->dmn, "Failed creating collision entry\n"); in dr_rule_create_collision_entry()
[all …]
/linux-5.10/drivers/net/usb/
Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
22 /* Rx status word */
38 /* SCSRs - System Control and Status Registers */
54 #define INT_STS_RX_STOP_ (0x00010000) /* RX Stopped */
59 #define INT_STS_RXDF_ (0x00000800) /* RX Dropped Frame */
77 #define HW_CFG_RXDOFF_ (0x00000600) /* RX Data Offset */
80 #define HW_CFG_DRP_ (0x00000040) /* Discard Errored RX Frame */
90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
126 #define AFC_CFG_HI_ (0x00FF0000) /* Auto Flow Ctrl High Level */
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
11 "ctrl": MDIO and PHY control and status region
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
[all …]
/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
59 /* program the RX pbl */ in sxgbe_dma_channel_init()
78 * same as TX/RX desc list in sxgbe_dma_channel_init()
80 dma_addr = dma_tx + ((t_rsize - 1) * SXGBE_DESC_SIZE_BYTES); in sxgbe_dma_channel_init()
84 dma_addr = dma_rx + ((r_rsize - 1) * SXGBE_DESC_SIZE_BYTES); in sxgbe_dma_channel_init()
88 writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
89 writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
91 /* Enable TX/RX interrupts */ in sxgbe_dma_channel_init()
107 /* Enable TX/RX interrupts */ in sxgbe_enable_dma_irq()
114 /* Disable TX/RX interrupts */ in sxgbe_disable_dma_irq()
[all …]

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