1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
52 	{ true, "RTES", "RX FSM Timeout Error" },
95 	{ true, "RXCES", "MTL RX Memory Error" },
96 	{ true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
97 	{ true, "RXUES", "MTL RX Memory Error" },
103 	{ true, "RPCES", "MTL RX Parser Memory Error" },
104 	{ true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
105 	{ true, "RPUES", "MTL RX Parser Memory Error" },
191 		return -EINVAL;  in dwmac5_safety_feat_config()
196 	value |= MRXPEE; /* MTL RX Parser ECC */  in dwmac5_safety_feat_config()
198 	value |= MRXEE; /* MTL RX FIFO ECC */  in dwmac5_safety_feat_config()
204 	value |= RPCEIE; /* RX Parser Memory Correctable Error */  in dwmac5_safety_feat_config()
206 	value |= RXCEIE; /* RX Memory Correctable Error */  in dwmac5_safety_feat_config()
251 		return -EINVAL;  in dwmac5_safety_feat_irq_status()
295 		return -EINVAL;  in dwmac5_safety_feat_dump()
297 		return -EINVAL;  in dwmac5_safety_feat_dump()
336 	for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {  in dwmac5_rxp_update_single_entry()
337 		int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;  in dwmac5_rxp_update_single_entry()
347 		val = *((u32 *)&entry->val + i);  in dwmac5_rxp_update_single_entry()
381 	for (i = count - 1; i >= 0; i--) {  in dwmac5_rxp_get_next_entry()
385 		if (!entry->in_use)  in dwmac5_rxp_get_next_entry()
388 		if (entry->in_hw)  in dwmac5_rxp_get_next_entry()
391 		if (entry->is_last)  in dwmac5_rxp_get_next_entry()
394 		if (entry->is_frag)  in dwmac5_rxp_get_next_entry()
397 		if (entry->prio < curr_prio)  in dwmac5_rxp_get_next_entry()
400 		if (entry->prio < min_prio) {  in dwmac5_rxp_get_next_entry()
401 			min_prio = entry->prio;  in dwmac5_rxp_get_next_entry()
420 	/* Force disable RX */  in dwmac5_rxp_config()
425 	/* Disable RX Parser */  in dwmac5_rxp_config()
433 		entry->in_hw = false;  in dwmac5_rxp_config()
442 		curr_prio = entry->prio;  in dwmac5_rxp_config()
443 		frag = entry->frag_ptr;  in dwmac5_rxp_config()
447 			entry->val.af = 0;  in dwmac5_rxp_config()
448 			entry->val.rf = 0;  in dwmac5_rxp_config()
449 			entry->val.nc = 1;  in dwmac5_rxp_config()
450 			entry->val.ok_index = nve + 2;  in dwmac5_rxp_config()
457 		entry->table_pos = nve++;  in dwmac5_rxp_config()
458 		entry->in_hw = true;  in dwmac5_rxp_config()
460 		if (frag && !frag->in_hw) {  in dwmac5_rxp_config()
464 			frag->table_pos = nve++;  in dwmac5_rxp_config()
465 			frag->in_hw = true;  in dwmac5_rxp_config()
475 		if (!entry->is_last)  in dwmac5_rxp_config()
482 		entry->table_pos = nve++;  in dwmac5_rxp_config()
490 	/* Enable RX Parser */  in dwmac5_rxp_config()
494 	/* Re-enable RX */  in dwmac5_rxp_config()
507 	if (!cfg->available)  in dwmac5_flex_pps_config()
508 		return -EINVAL;  in dwmac5_flex_pps_config()
510 		return -EBUSY;  in dwmac5_flex_pps_config()
512 		return -EINVAL;  in dwmac5_flex_pps_config()
527 	writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index));  in dwmac5_flex_pps_config()
530 		cfg->start.tv_nsec = (cfg->start.tv_nsec * 1000) / 465;  in dwmac5_flex_pps_config()
531 	writel(cfg->start.tv_nsec, ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index));  in dwmac5_flex_pps_config()
533 	period = cfg->period.tv_sec * 1000000000;  in dwmac5_flex_pps_config()
534 	period += cfg->period.tv_nsec;  in dwmac5_flex_pps_config()
539 		return -EINVAL;  in dwmac5_flex_pps_config()
541 	writel(period - 1, ioaddr + MAC_PPSx_INTERVAL(index));  in dwmac5_flex_pps_config()
545 		return -EINVAL;  in dwmac5_flex_pps_config()
547 	writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index));  in dwmac5_flex_pps_config()
556 	u32 ctrl;  in dwmac5_est_write()  local
560 	ctrl = (reg << ADDR_SHIFT);  in dwmac5_est_write()
561 	ctrl |= gcl ? 0 : GCRR;  in dwmac5_est_write()
563 	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);  in dwmac5_est_write()
565 	ctrl |= SRWO;  in dwmac5_est_write()
566 	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);  in dwmac5_est_write()
569 				  ctrl, !(ctrl & SRWO), 100, 5000);  in dwmac5_est_write()
575 	u32 speed, total_offset, offset, ctrl, ctr_low;  in dwmac5_est_configure()  local
586 		offset = 96 - (offset * 8);  in dwmac5_est_configure()
606 		return -EINVAL;  in dwmac5_est_configure()
611 	ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);  in dwmac5_est_configure()
612 	ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);  in dwmac5_est_configure()
613 	ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false);  in dwmac5_est_configure()
614 	ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);  in dwmac5_est_configure()
619 	for (i = 0; i < cfg->gcl_size; i++) {  in dwmac5_est_configure()
620 		ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i] + offset, true);  in dwmac5_est_configure()
627 	total_ctr = cfg->ctr[0] + cfg->ctr[1] * 1000000000ULL;  in dwmac5_est_configure()
637 	ctrl = readl(ioaddr + MTL_EST_CONTROL);  in dwmac5_est_configure()
638 	ctrl &= ~PTOV;  in dwmac5_est_configure()
639 	ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;  in dwmac5_est_configure()
640 	if (cfg->enable)  in dwmac5_est_configure()
641 		ctrl |= EEST | SSWL;  in dwmac5_est_configure()
643 		ctrl &= ~EEST;  in dwmac5_est_configure()
645 	writel(ctrl, ioaddr + MTL_EST_CONTROL);  in dwmac5_est_configure()
665 	value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;  in dwmac5_fpe_configure()