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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi16 compatible = "thead,c920", "riscv";
25 mmu-type = "riscv,sv48";
27 riscv,isa = "rv64imafdcv";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 riscv,cbom-block-size = <64>;
41 riscv,cbop-block-size = <64>;
42 riscv,cboz-block-size = <64>;
45 compatible = "riscv,cpu-intc";
52 compatible = "thead,c920", "riscv";
[all …]
H A Dsg2042-cpus.dtsi257 compatible = "thead,c920", "riscv";
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
274 mmu-type = "riscv,sv39";
277 compatible = "riscv,cpu-intc";
284 compatible = "thead,c920", "riscv";
286 riscv,isa = "rv64imafdc";
287 riscv,isa-base = "rv64i";
288 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
[all …]
H A Dcv180x-cpus.dtsi14 compatible = "thead,c906", "riscv";
23 mmu-type = "riscv,sv39";
24 riscv,isa = "rv64imafdc";
25 riscv,isa-base = "rv64i";
26 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
30 compatible = "riscv,cpu-intc";
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
67 - const: riscv
73 - const: riscv
74 - const: riscv # Simulator only
84 https://riscv.org/specifications/
87 - riscv,sv32
88 - riscv,sv39
89 - riscv,sv48
90 - riscv,sv57
91 - riscv,none
[all …]
/linux/drivers/gpu/drm/tegra/
H A Driscv.c11 #include "riscv.h"
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,aplic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
16 https://github.com/riscv/riscv-aia.
31 - const: riscv,aplic
46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
57 riscv,num-sources:
65 riscv,children:
78 riscv,delegation:
94 riscv,hart-indexes:
103 riscv,delegation: [ "riscv,children" ]
110 - riscv,num-sources
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H A Driscv,imsics.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
51 - const: riscv,imsics
75 to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
78 riscv,num-ids:
85 riscv,num-guest-ids:
92 riscv,num-ids property.
94 riscv,guest-index-bits:
101 riscv,hart-index-bits:
108 riscv,group-index-bits:
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/linux/arch/riscv/
H A DMakefile68 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
69 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
70 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
71 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
72 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
82 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
86 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
89 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
93 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\…
95 KBUILD_AFLAGS += -march=$(riscv-march-y)
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/linux/arch/riscv/boot/dts/spacemit/
H A Dk1.dtsi53 compatible = "spacemit,x60", "riscv";
56 …riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_z…
57 riscv,isa-base = "rv64i";
58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
63 riscv,cbom-block-size = <64>;
64 riscv,cbop-block-size = <64>;
65 riscv,cboz-block-size = <64>;
73 mmu-type = "riscv,sv39";
76 compatible = "riscv,cpu-intc";
83 compatible = "spacemit,x60", "riscv";
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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
27 mmu-type = "riscv,sv39";
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
45 compatible = "andestech,ax45mp", "riscv";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
52 mmu-type = "riscv,sv39";
64 "riscv,cpu-intc";
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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
42 - const: riscv,pci-iommu
84 compatible = "qemu,riscv-iommu", "riscv,iommu";
104 compatible = "qemu,riscv-iommu", "riscv,iommu";
114 compatible = "qemu,riscv-iommu", "riscv,iommu";
142 compatible = "pci1efd,edf1", "riscv,pci-iommu";
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux/arch/riscv/kernel/tests/
H A DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
35 endmenu # "arch/riscv/kernel runtime Testing"
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi23 compatible = "thead,c910", "riscv";
25 riscv,isa = "rv64imafdc";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
37 mmu-type = "riscv,sv39";
40 compatible = "riscv,cpu-intc";
47 compatible = "thead,c910", "riscv";
49 riscv,isa = "rv64imafdc";
50 riscv,isa-base = "rv64i";
51 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml322 Documentation/devicetree/bindings/riscv/cpus.yaml
325 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
370 - riscv,idle-state
381 riscv,sbi-suspend-param:
782 compatible = "riscv";
784 riscv,isa = "rv64imafdc";
785 mmu-type = "riscv,sv48";
791 compatible = "riscv,cpu-intc";
798 compatible = "riscv";
800 riscv,isa = "rv64imafdc";
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/linux/arch/riscv/kernel/
H A Dcpu.c54 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
70 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
83 if (!of_property_present(node, "riscv,isa-extensions")) in riscv_early_of_processor_hartid()
86 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || in riscv_early_of_processor_hartid()
87 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || in riscv_early_of_processor_hartid()
88 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { in riscv_early_of_processor_hartid()
97 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", in riscv_early_of_processor_hartid()
102 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_early_of_processor_hartid()
103 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", in riscv_early_of_processor_hartid()
130 if (of_device_is_compatible(node, "riscv")) { in riscv_of_parent_hartid()
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
20 in Documentation/devicetree/bindings/riscv/cpus.yaml
25 - riscv,timer
31 riscv,timer-cannot-wake-cpu:
46 compatible = "riscv,timer";
/linux/drivers/clocksource/
H A Dtimer-riscv.c11 #define pr_fmt(fmt) "riscv-timer: " fmt
26 #include <clocksource/timer-riscv.h>
178 pr_err("RISCV timer registration failed [%d]\n", error); in riscv_timer_init_common()
186 "riscv-timer", &riscv_clock_event); in riscv_timer_init_common()
198 "clockevents/riscv/timer:starting", in riscv_timer_init_common()
201 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_common()
229 child = of_find_compatible_node(NULL, NULL, "riscv,timer"); in riscv_timer_init_dt()
232 "riscv,timer-cannot-wake-cpu"); in riscv_timer_init_dt()
239 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
/linux/Documentation/arch/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux/tools/testing/kunit/qemu_configs/
H A Driscv.py11 …'Please ensure that qemu-system-riscv is installed, or edit the path in "qemu_configs/riscv.py"\n')
14 QEMU_ARCH = QemuArchParams(linux_arch='riscv',
23 kernel_path='arch/riscv/boot/Image',
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
34 mmu-type = "riscv,sv39";
36 riscv,isa = "rv64imafdc";
37 riscv,isa-base = "rv64i";
38 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
43 compatible = "riscv,cpu-intc";
50 compatible = "sifive,u74-mc", "riscv";
63 mmu-type = "riscv,sv39";
65 riscv,isa = "rv64imafdc";
66 riscv,isa-base = "rv64i";
[all …]
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
136 riscv,ndev = <511>;

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