| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | uncore-interconnect.json | 12 …n till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.…
21 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
31 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in Dir…
36 …"PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in Dire…
41 … "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
50 … "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
55 … "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
60 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
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| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | uncore-interconnect.json | 3 …. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access…
8 …. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access…
22 …n till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.…
31 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
41 … "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
50 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
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| /linux/arch/riscv/mm/ |
| H A D | dma-noncoherent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
131 void arch_setup_dma_ops(struct device *dev, bool coherent) in arch_setup_dma_ops() argument
133 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, in arch_setup_dma_ops()
135 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
139 WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC, in arch_setup_dma_ops()
140 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore-interconnect.json | 21 …ing for data returning from the memory controller. Accounts for coherent and non-coherent requests…
30 …are waiting for data return from memory controller. Account for coherent and non-coherent requests…
40 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
50 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
77 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
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| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore-interconnect.json | 21 …ing for data returning from the memory controller. Accounts for coherent and non-coherent requests…
30 …are waiting for data return from memory controller. Account for coherent and non-coherent requests…
40 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
50 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
77 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent requests at memory controller that w…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
32 …"BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is d…
42 … from its allocation in ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic.…
52 …"BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is d…
62 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
71 …"BriefDescription": "Counts number of all coherent Data Read entries. Does not include prefetches.…
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 … from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
|
| /linux/arch/mips/kernel/ |
| H A D | pm-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
26 * cps_nc_entry_fn - type of a generated non-coherent state entry function
28 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
30 * The code entering & exiting non-coherent states is generated at runtime
33 * core-specific code particularly for cache routines. If coupled_coherence
34 * is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
[all …]
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| /linux/drivers/cpuidle/ |
| H A D | cpuidle-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
16 STATE_WAIT = 0, /* MIPS wait instruction, coherent */
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
57 return -EINTR; in cps_nc_enter()
78 .name = "nc-wait",
79 .desc = "non-coherent MIPS wait",
86 .name = "clock-gated",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …d from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …d from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | uncore-interconnect.json | 3 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
22 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
58 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
|
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | uncore-interconnect.json | 3 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
39 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
|
| /linux/Documentation/core-api/ |
| H A D | dma-api.rst | 8 of the API (and actual examples), see Documentation/core-api/dma-api-howto.rst.
11 Part II describes extensions for supporting non-coherent memory
13 non-coherent platforms (this is usually only legacy platforms) you
16 Part I - DMA API
17 ----------------
19 To get the DMA API, you must #include <linux/dma-mapping.h>. This
27 Part Ia - Using large DMA-coherent buffers
28 ------------------------------------------
36 Coherent memory is memory for which a write by either the device or
42 This routine allocates a region of <size> bytes of coherent memory.
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| /linux/arch/mips/mm/ |
| H A D | dma-noncoherent.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org>
7 #include <linux/dma-direct.h>
8 #include <linux/dma-map-ops.h>
12 #include <asm/cpu-type.h>
18 * flush post-DMA.
20 * Warning on the terminology - Linux calls an uncached area coherent; MIPS
21 * terminology calls memory areas with hardware maintained coherency coherent.
24 * However this function is only called on non-I/O-coherent systems and only the
41 * the post-DMA flush/invalidate. in cpu_needs_post_dma_flush()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | uncore-interconnect.json | 12 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
|
| /linux/Documentation/driver-api/cxl/devices/ |
| H A D | device-types.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 covers some basic background on device types and on-device resources used by the platform and OS
20 ------
30 ---------
36 ---------
45 Type-1
46 ------
48 A Type-1 CXL device:
51 * Implements a fully coherent cache
52 * Allows Device-to-Host coherence and Host-to-Device snoops.
[all …]
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| /linux/include/linux/ |
| H A D | dma-map-ops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/dma-mapping.h>
74 #include <asm/dma-mapping.h>
78 if (dev->dma_ops) in get_dma_ops()
79 return dev->dma_ops; in get_dma_ops()
86 dev->dma_ops = dma_ops; in set_dma_ops()
104 if (dev && dev->cma_area) in dev_get_cma_area()
105 return dev->cma_area; in dev_get_cma_area()
133 return -ENOSYS; in dma_contiguous_reserve_area()
171 return -ENOSYS; in dma_declare_coherent_memory()
[all …]
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| /linux/Documentation/arch/xtensa/ |
| H A D | atomctl.rst | 9 1. With and without an Coherent Cache Controller which
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, though non-MX controllers likely
29 CUSTOMER-WARNING:
45 Values WB - Write Back WT - Write Thru BY - Bypass
|
| /linux/drivers/ras/amd/atl/ |
| H A D | internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 /* Maximum possible number of Coherent Stations within a single Data Fabric. */
111 * divisible by 5. Power-of-two interleave modes are handled
148 * These masks operate on the 16-bit Coherent Station IDs,
157 * Least-significant bit of Node ID portion of the
158 * system-wide Coherent Station Fabric ID.
163 * Least-significant bit of Die portion of the Node ID.
165 * to the Coherent Station Fabric ID.
170 * Least-significant bit of Socket portion of the Node ID.
172 * to the Coherent Station Fabric ID.
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-cp11x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-interconnect.json | 3 … "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
9 …"PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. …
31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | uncore-interconnect.json | 3 … "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
9 …"PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. …
31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
[all …]
|
| /linux/Documentation/arch/arm/ |
| H A D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
40 The mechanism presented in this document describes a coherent memory
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
[all …]
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| /linux/include/sound/ |
| H A D | memalloc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include <linux/dma-direction.h>
33 #define SNDRV_DMA_TYPE_CONTINUOUS 1 /* continuous no-DMA memory */
35 #define SNDRV_DMA_TYPE_DEV_WC 5 /* continuous write-combined */
37 #define SNDRV_DMA_TYPE_DEV_IRAM 4 /* generic device iram-buffer */
42 #define SNDRV_DMA_TYPE_NONCONTIG 8 /* non-coherent SG buffer */
43 #define SNDRV_DMA_TYPE_NONCOHERENT 9 /* non-coherent buffer */
46 #define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */
48 #define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */
68 return (size + PAGE_SIZE - 1) >> PAGE_SHIFT; in snd_sgbuf_aligned_pages()
[all …]
|