17e74ece3SIan Rogers[ 27e74ece3SIan Rogers { 37e74ece3SIan Rogers "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.", 4bf0dd1f4SIan Rogers "Counter": "1", 57e74ece3SIan Rogers "EventCode": "0x84", 67e74ece3SIan Rogers "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 77e74ece3SIan Rogers "PerPkg": "1", 87e74ece3SIan Rogers "UMask": "0x1", 97e74ece3SIan Rogers "Unit": "ARB" 107e74ece3SIan Rogers }, 117e74ece3SIan Rogers { 12bf0dd1f4SIan Rogers "BriefDescription": "Each cycle counts number of any coherent requests at memory controller that were issued by any core.", 13bf0dd1f4SIan Rogers "Counter": "0", 147e74ece3SIan Rogers "EventCode": "0x85", 157e74ece3SIan Rogers "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", 16bf0dd1f4SIan Rogers "Experimental": "1", 177e74ece3SIan Rogers "PerPkg": "1", 187e74ece3SIan Rogers "UMask": "0x1", 197e74ece3SIan Rogers "Unit": "ARB" 207e74ece3SIan Rogers }, 217e74ece3SIan Rogers { 22bf0dd1f4SIan Rogers "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.", 23bf0dd1f4SIan Rogers "Counter": "0", 247e74ece3SIan Rogers "EventCode": "0x85", 257e74ece3SIan Rogers "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", 26bf0dd1f4SIan Rogers "Experimental": "1", 277e74ece3SIan Rogers "PerPkg": "1", 287e74ece3SIan Rogers "UMask": "0x2", 297e74ece3SIan Rogers "Unit": "ARB" 307e74ece3SIan Rogers }, 317e74ece3SIan Rogers { 32bf0dd1f4SIan Rogers "BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches.", 33bf0dd1f4SIan Rogers "Counter": "0", 347e74ece3SIan Rogers "EventCode": "0x80", 357e74ece3SIan Rogers "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", 36bf0dd1f4SIan Rogers "Experimental": "1", 377e74ece3SIan Rogers "PerPkg": "1", 387e74ece3SIan Rogers "UMask": "0x2", 397e74ece3SIan Rogers "Unit": "ARB" 407e74ece3SIan Rogers }, 417e74ece3SIan Rogers { 42bf0dd1f4SIan Rogers "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic.", 43bf0dd1f4SIan Rogers "Counter": "0", 447e74ece3SIan Rogers "EventCode": "0x80", 457e74ece3SIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 46bf0dd1f4SIan Rogers "Experimental": "1", 477e74ece3SIan Rogers "PerPkg": "1", 487e74ece3SIan Rogers "UMask": "0x1", 497e74ece3SIan Rogers "Unit": "ARB" 507e74ece3SIan Rogers }, 517e74ece3SIan Rogers { 52bf0dd1f4SIan Rogers "BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches.", 53bf0dd1f4SIan Rogers "Counter": "0", 547e74ece3SIan Rogers "EventCode": "0x80", 557e74ece3SIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", 56bf0dd1f4SIan Rogers "Experimental": "1", 577e74ece3SIan Rogers "PerPkg": "1", 587e74ece3SIan Rogers "UMask": "0x2", 597e74ece3SIan Rogers "Unit": "ARB" 607e74ece3SIan Rogers }, 617e74ece3SIan Rogers { 627e74ece3SIan Rogers "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", 63bf0dd1f4SIan Rogers "Counter": "1", 647e74ece3SIan Rogers "EventCode": "0x81", 657e74ece3SIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 667e74ece3SIan Rogers "PerPkg": "1", 677e74ece3SIan Rogers "UMask": "0x1", 687e74ece3SIan Rogers "Unit": "ARB" 697e74ece3SIan Rogers }, 707e74ece3SIan Rogers { 71bf0dd1f4SIan Rogers "BriefDescription": "Counts number of all coherent Data Read entries. Does not include prefetches.", 72bf0dd1f4SIan Rogers "Counter": "0,1", 737e74ece3SIan Rogers "EventCode": "0x81", 747e74ece3SIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.RD", 75bf0dd1f4SIan Rogers "Experimental": "1", 767e74ece3SIan Rogers "PerPkg": "1", 777e74ece3SIan Rogers "UMask": "0x2", 787e74ece3SIan Rogers "Unit": "ARB" 797e74ece3SIan Rogers } 807e74ece3SIan Rogers] 81