| /linux/arch/csky/abiv2/inc/abi/ |
| H A D | entry.h | 73 mtcr a0, epc
75 mtcr a0, epsr
78 mtcr a0, usp
79 mtcr a0, ss0
87 mtcr a0, cr14
148 mtcr a0, cr14
192 mtcr lr, cr14
229 mtcr \rx, cr<4, 15>
233 mtcr \rx, cr<8, 15>
249 mtcr r6, psr
[all …]
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| H A D | ckmmu.h | 16 mtcr("cr<0, 15>", value); in write_mmu_index()
31 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
41 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
51 mtcr("cr<30, 15>", value); in write_mmu_msa0()
61 mtcr("cr<31, 15>", value); in write_mmu_msa1()
69 mtcr("cr<8, 15>", 0x80000000); in tlb_probe()
74 mtcr("cr<8, 15>", 0x40000000); in tlb_read()
88 mtcr("cr<8, 15>", 0x04000000); in tlb_invalid_all()
109 mtcr("cr<8, 15>", 0x02000000); in tlb_invalid_indexed()
123 "mtcr %1, cr<28, 15> \n" in setup_pgd()
[all …]
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| H A D | fpu.h | 12 static inline void init_fpu(void) { mtcr("cr<1, 2>", 0); } in init_fpu()
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| /linux/arch/csky/abiv1/inc/abi/ |
| H A D | entry.h | 21 mtcr sp, usp
26 mtcr sp, ss0
31 mtcr r13, ss2
84 mtcr a0, epc
86 mtcr a0, epsr
90 mtcr a0, ss1
156 mtcr r6, psr
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| /linux/drivers/clocksource/ |
| H A D | timer-mp-csky.c | 23 mtcr(PTIM_LVR, delta); in csky_mptimer_set_next_event()
30 mtcr(PTIM_CTLR, 0); in csky_mptimer_shutdown()
37 mtcr(PTIM_CTLR, 1); in csky_mptimer_oneshot()
44 mtcr(PTIM_CTLR, 0); in csky_mptimer_oneshot_stopped()
66 mtcr(PTIM_TSR, 0); in csky_timer_interrupt()
128 * The regs is accessed by cpu instruction: mfcr/mtcr instead of in csky_mptimer_init()
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| /linux/arch/csky/mm/ |
| H A D | cachev1.c | 27 mtcr("cr22", i); in cache_op_line()
28 mtcr("cr17", val); in cache_op_line()
34 mtcr("cr17", value | CACHE_CLR); in cache_op_all()
38 mtcr("cr24", value | CACHE_CLR); in cache_op_all()
72 mtcr("cr24", val); in cache_op_range()
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| H A D | cachev2.c | 19 mtcr("cr17", INS_CACHE|CACHE_INV); in local_icache_inv_all()
42 mtcr("cr22", i); in cache_op_line()
43 mtcr("cr17", val); in cache_op_line()
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| /linux/arch/csky/kernel/ |
| H A D | head.S | 27 mtcr r6, cr<31, 15>
32 mtcr r6, cr<28, 15>
33 mtcr r6, cr<29, 15>
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| H A D | atomic.S | 53 mtcr a3, epc
55 mtcr a3, epsr
57 mtcr a3, usp
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| H A D | smp.c | 220 mtcr("cr17", 0x22); in __cpu_up()
227 mtcr("cr<29, 0>", mask); in __cpu_up()
247 mtcr("cr31", secondary_hint); in csky_start_secondary()
248 mtcr("cr<21, 1>", secondary_hint2); in csky_start_secondary()
249 mtcr("cr18", secondary_ccr); in csky_start_secondary()
251 mtcr("vbr", vec_base); in csky_start_secondary()
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| H A D | traps.c | 52 mtcr("vbr", vec_base); in pre_trap_init()
77 mtcr("cr<28, 0>", virt_to_phys(vec_base)); in trap_init()
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| /linux/arch/csky/abiv2/ |
| H A D | fpu.c | 17 * - mtcr %a, cr<1, 2>
18 * - mtcr %a, cr<2, 2>
57 mtcr("cr<1, 2>", regx); in fpu_libc_helper()
59 mtcr("cr<2, 2>", regx); in fpu_libc_helper()
222 mtcr("cr<1, 2>", tmp1); in restore_from_user_fp()
223 mtcr("cr<2, 2>", tmp2); in restore_from_user_fp()
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| /linux/arch/csky/include/asm/ |
| H A D | reg_ops.h | 17 #define mtcr(reg, val) \ macro
20 "mtcr %0, "reg"\n" \
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| H A D | irqflags.h | 37 mtcr("psr", flags); in arch_local_irq_restore()
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| /linux/arch/powerpc/kernel/ |
| H A D | entry_32.S | 156 mtcr r5
162 3: mtcr r5
221 mtcr r10
284 mtcr r3
335 mtcr r6
349 mtcr r6
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| H A D | rtas_entry.S | 85 mtcr r0
160 mtcr r4
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| /linux/arch/powerpc/lib/ |
| H A D | test_emulate_step_exec_instr.S | 70 mtcr r0
139 mtcr r0
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| /linux/arch/powerpc/kvm/ |
| H A D | book3s_rmhandlers.S | 62 2: mtcr r12
133 mtcr r12
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| H A D | tm.S | 137 mtcr r6
307 mtcr r6
357 mtcr r6
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| H A D | booke_interrupts.S | 90 mtcr r3
95 mtcr r3
334 mtcr r5
472 mtcr r5
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| H A D | book3s_64_entry.S | 236 mtcr r1
257 mtcr r1
332 mtcr r4
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| H A D | fpu.S | 125 mtcr r6
217 mtcr r6; \
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | csky,mptimer.yaml | 15 accessed by cpu co-processor 4 registers with mtcr/mfcr.
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| /linux/arch/powerpc/boot/ |
| H A D | opal-calls.S | 59 mtcr r11;
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| /linux/tools/testing/selftests/powerpc/switch_endian/ |
| H A D | switch_endian_test.S | 26 mtcr r3
|