/linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
H A D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 41 "BriefDescription": "All L2 Cache Misses", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 59 "BriefDescription": "L2 Cache Misses from L2 HWPF", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", [all...] |
/linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
H A D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 41 "BriefDescription": "All L2 Cache Misses", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 59 "BriefDescription": "L2 Cache Misses from L2 HWPF", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", [all...] |
/linux/tools/perf/pmu-events/arch/x86/haswellx/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 12 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 16 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 52 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 69 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 78 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 87 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses [all...] |
/linux/tools/perf/pmu-events/arch/x86/haswell/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 12 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 16 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 52 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 69 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 78 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 87 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses [all...] |
/linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
H A D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 41 "BriefDescription": "All L2 Cache Misses", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", [all...] |
/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
H A D | memory.json | 40 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.", 46 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.", 52 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.", 58 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.", 64 "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.", 70 "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.", 76 "BriefDescription": "L1 DTLB misses with L2 DTLB misses (pag [all...] |
H A D | recommended.json | 23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).", 29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).", 41 "BriefDescription": "All L2 cache misses.", 47 "BriefDescription": "L2 cache misses from L1 instruction cache misses.", 53 "BriefDescription": "L2 cache misses from L1 data cache misses.", 59 "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.", 71 "BriefDescription": "L2 cache hits from L1 instruction cache misses.", 77 "BriefDescription": "L2 cache hits from L1 data cache misses [all...] |
/linux/tools/perf/pmu-events/arch/x86/broadwell/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 8 "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 21 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", 29 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", 51 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 61 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 71 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", 86 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 91 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 104 "BriefDescription": "Store misses tha [all...] |
/linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 8 "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 21 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", 29 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", 51 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 61 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 71 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", 86 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 91 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 104 "BriefDescription": "Store misses tha [all...] |
/linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 8 "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 21 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", 29 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", 51 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 61 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 71 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", 86 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 91 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 104 "BriefDescription": "Store misses tha [all...] |
/linux/tools/perf/pmu-events/arch/powerpc/power10/ |
H A D | metrics.json | 292 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is in the store unit outside of handling store misses or other special store operations", 586 "BriefDescription": "Percentage of ITLB misses per completed run instruction", 599 "BriefDescription": "Percentage of DERAT misses with 4k page size per completed instruction", 606 "BriefDescription": "Percentage of DERAT misses with 64k page size per completed instruction", 613 "BriefDescription": "Percentage of ICache misses that were reloaded from the L2", 620 "BriefDescription": "Percentage of ICache misses that were reloaded from the L3", 627 "BriefDescription": "Percentage of ICache misses that were reloaded from local memory", 634 "BriefDescription": "Percentage of ICache misses that were reloaded from remote memory", 641 "BriefDescription": "Percentage of ICache misses that were reloaded from distant memory", 689 "BriefDescription": "Percentage of DERAT misses pe [all...] |
H A D | marked.json | 15 "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 25 "BriefDescription": "Marked Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 95 "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 120 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 145 "BriefDescription": "Marked Data TLB reload (after a miss) page size 2M, which implies Radix Page Table translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 160 "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 200 "BriefDescription": "Marked Erat Miss (Data TLB Access) All page sizes. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses [all...] |
/linux/tools/perf/pmu-events/arch/riscv/sifive/p550/ |
H A D | memory.json | 5 "BriefDescription": "Counts instruction cache misses" 10 "BriefDescription": "Counts data cache misses" 20 "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" 25 "BriefDescription": "Counts Data TLB misses caused by data address translation requests" 30 "BriefDescription": "Counts Unified TLB misses caused by address translation requests" 40 "BriefDescription": "Counts Page Table Entry cache misses"
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/linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
H A D | virtual-memory.json | 11 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.", 19 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", 28 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.", 37 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", 46 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", 72 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.", 80 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", 89 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", 98 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.", 107 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses t [all...] |
/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
H A D | virtual-memory.json | 11 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.", 19 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", 28 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.", 37 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", 46 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", 72 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.", 80 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", 89 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", 98 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.", 107 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses t [all...] |
/linux/tools/perf/pmu-events/arch/riscv/sifive/p650/ |
H A D | memory.json | 5 "BriefDescription": "Counts instruction cache misses" 10 "BriefDescription": "Counts data cache misses" 20 "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" 25 "BriefDescription": "Counts Data TLB misses caused by data address translation requests" 30 "BriefDescription": "Counts Unified TLB misses caused by address translation requests" 40 "BriefDescription": "Counts Page Table Entry cache misses"
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/linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
H A D | virtual-memory.json | 15 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", 33 "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", 47 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 65 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 100 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", 104 "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", 109 "BriefDescription": "Misses at all ITLB levels that cause page walks", 113 "PublicDescription": "Misses in all ITLB levels that cause page walks.", 127 "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 131 "PublicDescription": "Misses i [all...] |
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ |
H A D | l2_cache.json | 4 "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." 8 "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 16 "PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 20 "PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 24 "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 28 "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 60 "PublicDescription": "Counts level 2 cache demand accesses from any load/store operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 68 "PublicDescription": "Counts cache line misses in the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
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/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ |
H A D | l2_cache.json | 4 "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." 8 "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 20 "PublicDescription": "Counts accesses to the level 2 cache due to instruction accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level instruction cache." 24 "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 instruction cache." 28 "PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 32 "PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 36 "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 40 "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 64 "PublicDescription": "Counts level 2 cache demand accesses from any load/store operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
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/linux/tools/perf/pmu-events/arch/x86/grandridge/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", 11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", 19 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", 28 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", 46 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.", 54 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", 62 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.", 71 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.", 97 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", 105 "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses t [all...] |
/linux/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/ |
H A D | memory.json | 5 "BriefDescription": "Counts instruction cache misses" 10 "BriefDescription": "Counts data cache misses" 20 "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" 25 "BriefDescription": "Counts Data TLB misses caused by data address translation requests" 30 "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
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/linux/tools/perf/pmu-events/arch/riscv/sifive/bullet/ |
H A D | memory.json | 5 "BriefDescription": "Counts instruction cache misses" 10 "BriefDescription": "Counts data cache misses" 20 "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" 25 "BriefDescription": "Counts Data TLB misses caused by data address translation requests" 30 "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
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/linux/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/ |
H A D | memory.json | 5 "BriefDescription": "Counts instruction cache misses" 10 "BriefDescription": "Counts data cache misses" 20 "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" 25 "BriefDescription": "Counts Data TLB misses caused by data address translation requests" 30 "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
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/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
H A D | virtual-memory.json | 31 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", 49 "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", 63 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 81 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 116 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", 120 "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", 125 "BriefDescription": "Misses at all ITLB levels that cause page walks", 129 "PublicDescription": "Misses in all ITLB levels that cause page walks.", 143 "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 147 "PublicDescription": "Misses i [all...] |
/linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.", 20 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", 32 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 37 "BriefDescription": "Store misses in all DTLB levels that cause page walks.", 53 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", 85 "BriefDescription": "Misses at all ITLB levels that cause page walks.", 101 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", 113 "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
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