xref: /linux/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json (revision 4f9786035f9e519db41375818e1d0b5f20da2f10) 
1*2e3a13d6SEric Lin[
2*2e3a13d6SEric Lin  {
3*2e3a13d6SEric Lin    "EventName": "ICACHE_MISS",
4*2e3a13d6SEric Lin    "EventCode": "0x102",
5*2e3a13d6SEric Lin    "BriefDescription": "Counts instruction cache misses"
6*2e3a13d6SEric Lin  },
7*2e3a13d6SEric Lin  {
8*2e3a13d6SEric Lin    "EventName": "DCACHE_MISS",
9*2e3a13d6SEric Lin    "EventCode": "0x202",
10*2e3a13d6SEric Lin    "BriefDescription": "Counts data cache misses"
11*2e3a13d6SEric Lin  },
12*2e3a13d6SEric Lin  {
13*2e3a13d6SEric Lin    "EventName": "DCACHE_RELEASE",
14*2e3a13d6SEric Lin    "EventCode": "0x402",
15*2e3a13d6SEric Lin    "BriefDescription": "Counts writeback requests from the data cache"
16*2e3a13d6SEric Lin  },
17*2e3a13d6SEric Lin  {
18*2e3a13d6SEric Lin    "EventName": "ITLB_MISS",
19*2e3a13d6SEric Lin    "EventCode": "0x802",
20*2e3a13d6SEric Lin    "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
21*2e3a13d6SEric Lin  },
22*2e3a13d6SEric Lin  {
23*2e3a13d6SEric Lin    "EventName": "DTLB_MISS",
24*2e3a13d6SEric Lin    "EventCode": "0x1002",
25*2e3a13d6SEric Lin    "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
26*2e3a13d6SEric Lin  },
27*2e3a13d6SEric Lin  {
28*2e3a13d6SEric Lin    "EventName": "UTLB_MISS",
29*2e3a13d6SEric Lin    "EventCode": "0x2002",
30*2e3a13d6SEric Lin    "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
31*2e3a13d6SEric Lin  },
32*2e3a13d6SEric Lin  {
33*2e3a13d6SEric Lin    "EventName": "UTLB_HIT",
34*2e3a13d6SEric Lin    "EventCode": "0x4002",
35*2e3a13d6SEric Lin    "BriefDescription": "Counts Unified TLB hits for address translation requests"
36*2e3a13d6SEric Lin  },
37*2e3a13d6SEric Lin  {
38*2e3a13d6SEric Lin    "EventName": "PTE_CACHE_MISS",
39*2e3a13d6SEric Lin    "EventCode": "0x8002",
40*2e3a13d6SEric Lin    "BriefDescription": "Counts Page Table Entry cache misses"
41*2e3a13d6SEric Lin  },
42*2e3a13d6SEric Lin  {
43*2e3a13d6SEric Lin    "EventName": "PTE_CACHE_HIT",
44*2e3a13d6SEric Lin    "EventCode": "0x10002",
45*2e3a13d6SEric Lin    "BriefDescription": "Counts Page Table Entry cache hits"
46*2e3a13d6SEric Lin  }
47*2e3a13d6SEric Lin]
48