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/linux-5.10/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Alexandre Torgue <alexandre.torgue@st.com>
12 - Christophe Roullier <christophe.roullier@st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: "snps,dwmac.yaml#"
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Dimx-dwmac.txt1 IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
9 - compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
10 and "snps,dwmac-5.10a" to select IP version.
11 - clocks: Must contain a phandle for each entry in clock-names.
12 - clock-names: Should be "stmmaceth" for the host clock.
13 Should be "pclk" for the MAC apb clock.
14 Should be "ptp_ref" for the MAC timer clock.
15 Should be "tx" for the MAC RGMII TX clock:
17 - "mem" clock is required for imx8dxl platform.
18 - "mem" clock is not required for imx8mp platform.
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
23 transformer. This device interfaces directly to the MAC layer through the
34 ti,min-output-impedance:
37 MAC Interface Impedance control to set the programmable output impedance
[all …]
Dmediatek-dwmac.txt9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
14 Should be "macirq" for the main MAC IRQ
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
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Dsti-dwmac.txt10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 MAC can generate it.
23 - st,tx-retime-src: This specifies which clk is wired up to the mac for
24 retimeing tx lines. This is totally board dependent and can take one of the
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/linux-5.10/drivers/net/ethernet/faraday/
Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
47 /* Min number of tx ring entries before stopping queue */
66 /* Tx ring */
90 struct clk *clk; member
93 struct clk *rclk;
116 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
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/linux-5.10/drivers/net/ethernet/
Dethoc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
8 * Written by Thierry Reding <thierry.reding@avionic-design.de>
11 #include <linux/dma-mapping.h>
13 #include <linux/clk.h>
64 #define MODER_NBO (1 << 8) /* no back-off */
133 /* TX buffer descriptor */
141 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
145 #define TX_BD_READY (1 << 15) /* TX buffer ready */
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Dlantiq_xrx200.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
14 #include <linux/clk.h>
27 /* cpu port mac */
42 /* Remove Layer-2 header from packets from PMAC to DMA */
66 struct clk *clk; member
79 return __raw_readl(priv->pmac_reg + offset); in xrx200_pmac_r32()
84 __raw_writel(val, priv->pmac_reg + offset); in xrx200_pmac_w32()
103 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; in xrx200_flush_dma()
105 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) in xrx200_flush_dma()
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/linux-5.10/drivers/net/ethernet/nxp/
Dlpc_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
23 #include <linux/soc/nxp/lpc32xx-misc.h>
25 #define MODNAME "lpc-eth"
35 * Ethernet MAC controller Register offsets
317 if (dev && dev->of_node) { in lpc_phy_interface_mode()
318 const char *mode = of_get_property(dev->of_node, in lpc_phy_interface_mode()
319 "phy-mode", NULL); in lpc_phy_interface_mode()
328 if (dev && dev->of_node) in use_iram_for_net()
329 return of_property_read_bool(dev->of_node, "use-iram"); in use_iram_for_net()
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/linux-5.10/drivers/net/ethernet/allwinner/
Dsun4i-emac.c4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
15 #include <linux/clk.h>
33 #include "sun4i-emac.h"
35 #define DRV_NAME "sun4i-emac"
40 static int debug = -1; /* defaults above */;
72 struct clk *clk; member
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
100 if (db->speed == SPEED_100) in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
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/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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/linux-5.10/drivers/net/ethernet/socionext/
Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
37 /* MAC Register Group */
38 #define AVE_TXCR 0x200 /* TX Setup */
40 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
41 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
50 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
68 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
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/linux-5.10/drivers/net/ethernet/qualcomm/emac/
Demac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
19 #include "emac-mac.h"
20 #include "emac-phy.h"
21 #include "emac-sgmii.h"
85 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
91 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
101 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx()
102 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx()
110 irq->mask |= rx_q->intr; in emac_napi_rtx()
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/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h35 #define NTXRATE 64 /* # tx MPDUs rate is reported for */
37 /* Maximum wait time for a MAC suspend */
48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
65 #define SW_TIMER_MAC_STAT_UPD 30 /* periodic MAC stats update */
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
[all …]
/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
26 /* General notes on dwmac-sun8i:
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
37 * @soc_has_internal_phy: Does the MAC embed an internal PHY
38 * @support_mii: Does the MAC handle MII
39 * @support_rmii: Does the MAC handle RMII
40 * @support_rgmii: Does the MAC handle RGMII
[all …]
Ddwmac-oxnas.c1 // SPDX-License-Identifier: GPL-2.0-only
53 struct clk *clk; member
64 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
68 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
72 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
74 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
82 /* set auto switch tx clock source */ in oxnas_dwmac_init()
84 /* enable tx & rx vardelay */ in oxnas_dwmac_init()
91 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
93 /* set tx & rx vardelay */ in oxnas_dwmac_init()
[all …]
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
38 *------------------------------------------
40 *------------------------------------------
42 *------------------------------------------
44 *------------------------------------------
46 *------------------------------------------
48 *------------------------------------------
64 * ---------------------------------------------------------------------------
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/linux-5.10/drivers/net/ethernet/broadcom/
Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
29 * hardware maximum rx/tx packet size including FCS, max mtu is
199 /* mac irq, rx_dma irq, tx_dma irq */
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
247 /* dma channel id for tx */
250 /* number of dma desc in tx ring */
259 /* number of available descriptor for tx */
262 /* next tx descriptor avaiable */
[all …]
/linux-5.10/drivers/net/ethernet/freescale/
Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
40 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
41 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
43 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
44 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
45 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
76 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
[all …]
/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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/linux-5.10/drivers/net/ethernet/atheros/
Dag71xx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Atheros AR71xx built-in ethernet mac driver
11 * David Bauer <mail@david-bauer.net>
14 * Hauke Mehrtens <hauke@hauke-m.de>
15 * Johann Neuhauser <johann@it-neuhauser.de>
17 * Jo-Philipp Wich <jo@mein.io>
38 #include <linux/clk.h>
41 /* For our NAPI weight bigger does *NOT* mean better - it means more
42 * D-cache misses and lots more wasted cycles than we'll ever
69 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
[all …]
/linux-5.10/drivers/net/ethernet/smsc/
Dsmsc911x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2004-2008 SMSC
5 * Copyright (C) 2005-2008 ARM
22 #include <linux/clk.h>
57 #define SMSC_MDIONAME "smsc911x-mdio"
58 #define SMSC_DRV_VERSION "2008-10-21"
142 struct clk *clk; member
146 #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
150 if (pdata->config.flags & SMSC911X_USE_32BIT) in __smsc911x_reg_read()
151 return readl(pdata->ioaddr + reg); in __smsc911x_reg_read()
[all …]
/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
/linux-5.10/drivers/net/ethernet/aurora/
Dnb8800.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Driver for tangox SMP864x/SMP865x/SMP867x/SMP868x builtin Ethernet Mac.
22 #include <linux/dma-mapping.h>
37 return readb_relaxed(priv->base + reg); in nb8800_readb()
42 return readl_relaxed(priv->base + reg); in nb8800_readl()
47 writeb_relaxed(val, priv->base + reg); in nb8800_writeb()
52 writew_relaxed(val, priv->base + reg); in nb8800_writew()
57 writel_relaxed(val, priv->base + reg); in nb8800_writel()
114 struct nb8800_priv *priv = bus->priv; in nb8800_mdio_wait()
117 return readl_poll_timeout_atomic(priv->base + NB8800_MDIO_CMD, in nb8800_mdio_wait()
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