Lines Matching +full:mac +full:- +full:clk +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
37 /* MAC Register Group */
38 #define AVE_TXCR 0x200 /* TX Setup */
40 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
41 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
50 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
68 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
71 #define AVE_TXDM_SIZE_64 0x0ba0 /* Tx Descriptor Memory Size 3KB */
77 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
80 #define AVE_TXDM_SIZE_32 0x07c0 /* Tx Descriptor Memory Size 2KB */
92 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
102 #define AVE_GI_TX BIT(16) /* Tx complete */
117 #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */
132 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
135 #define AVE_TXDC_SIZE GENMASK(27, 16) /* Size of Tx descriptor */
152 /* TX */
175 #define AVE_PFNUM_MULTICAST 11 /* No.11-17 */
188 #define AVE_NR_TXDESC 64 /* Tx descriptor */
208 #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit)
256 struct clk *clk[AVE_MAX_CLKS]; member
278 struct ave_desc_info tx; member
302 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) in ave_desc_read()
303 + entry * priv->desc_size + offset; in ave_desc_read()
305 return readl(priv->base + addr); in ave_desc_read()
320 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr) in ave_desc_write()
321 + entry * priv->desc_size + offset; in ave_desc_write()
323 writel(val, priv->base + addr); in ave_desc_write()
350 ret = readl(priv->base + AVE_GIMR); in ave_irq_disable_all()
351 writel(0, priv->base + AVE_GIMR); in ave_irq_disable_all()
360 writel(val, priv->base + AVE_GIMR); in ave_irq_restore()
367 writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR); in ave_irq_enable()
368 writel(bitflag, priv->base + AVE_GISR); in ave_irq_enable()
378 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); in ave_hw_write_macaddr()
379 writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); in ave_hw_write_macaddr()
387 vr = readl(priv->base + AVE_VR); in ave_hw_read_version()
396 struct device *dev = ndev->dev.parent; in ave_ethtool_get_drvinfo()
398 strlcpy(info->driver, dev->driver->name, sizeof(info->driver)); in ave_ethtool_get_drvinfo()
399 strlcpy(info->bus_info, dev_name(dev), sizeof(info->bus_info)); in ave_ethtool_get_drvinfo()
400 ave_hw_read_version(ndev, info->fw_version, sizeof(info->fw_version)); in ave_ethtool_get_drvinfo()
407 return priv->msg_enable; in ave_ethtool_get_msglevel()
414 priv->msg_enable = val; in ave_ethtool_set_msglevel()
420 wol->supported = 0; in ave_ethtool_get_wol()
421 wol->wolopts = 0; in ave_ethtool_get_wol()
423 if (ndev->phydev) in ave_ethtool_get_wol()
424 phy_ethtool_get_wol(ndev->phydev, wol); in ave_ethtool_get_wol()
430 if (!ndev->phydev || in __ave_ethtool_set_wol()
431 (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))) in __ave_ethtool_set_wol()
432 return -EOPNOTSUPP; in __ave_ethtool_set_wol()
434 return phy_ethtool_set_wol(ndev->phydev, wol); in __ave_ethtool_set_wol()
444 device_set_wakeup_enable(&ndev->dev, !!wol->wolopts); in ave_ethtool_set_wol()
454 pause->autoneg = priv->pause_auto; in ave_ethtool_get_pauseparam()
455 pause->rx_pause = priv->pause_rx; in ave_ethtool_get_pauseparam()
456 pause->tx_pause = priv->pause_tx; in ave_ethtool_get_pauseparam()
463 struct phy_device *phydev = ndev->phydev; in ave_ethtool_set_pauseparam()
466 return -EINVAL; in ave_ethtool_set_pauseparam()
468 priv->pause_auto = pause->autoneg; in ave_ethtool_set_pauseparam()
469 priv->pause_rx = pause->rx_pause; in ave_ethtool_set_pauseparam()
470 priv->pause_tx = pause->tx_pause; in ave_ethtool_set_pauseparam()
472 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); in ave_ethtool_set_pauseparam()
493 struct net_device *ndev = bus->priv; in ave_mdiobus_read()
501 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); in ave_mdiobus_read()
504 mdioctl = readl(priv->base + AVE_MDIOCTR); in ave_mdiobus_read()
506 priv->base + AVE_MDIOCTR); in ave_mdiobus_read()
508 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, in ave_mdiobus_read()
516 return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0); in ave_mdiobus_read()
522 struct net_device *ndev = bus->priv; in ave_mdiobus_write()
530 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); in ave_mdiobus_write()
533 writel(val, priv->base + AVE_MDIOWDR); in ave_mdiobus_write()
536 mdioctl = readl(priv->base + AVE_MDIOCTR); in ave_mdiobus_write()
538 priv->base + AVE_MDIOCTR); in ave_mdiobus_write()
540 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, in ave_mdiobus_write()
555 map_addr = dma_map_single(ndev->dev.parent, ptr, len, dir); in ave_dma_map()
556 if (unlikely(dma_mapping_error(ndev->dev.parent, map_addr))) in ave_dma_map()
557 return -ENOMEM; in ave_dma_map()
559 desc->skbs_dma = map_addr; in ave_dma_map()
560 desc->skbs_dmalen = len; in ave_dma_map()
569 if (!desc->skbs_dma) in ave_dma_unmap()
572 dma_unmap_single(ndev->dev.parent, in ave_dma_unmap()
573 desc->skbs_dma, desc->skbs_dmalen, dir); in ave_dma_unmap()
574 desc->skbs_dma = 0; in ave_dma_unmap()
585 skb = priv->rx.desc[entry].skbs; in ave_rxdesc_prepare()
590 return -ENOMEM; in ave_rxdesc_prepare()
592 skb->data += AVE_FRAME_HEADROOM; in ave_rxdesc_prepare()
593 skb->tail += AVE_FRAME_HEADROOM; in ave_rxdesc_prepare()
602 * - Rx buffer address is 4 byte aligned. in ave_rxdesc_prepare()
603 * - Rx buffer begins with 2 byte headroom, and data will be put from in ave_rxdesc_prepare()
609 ret = ave_dma_map(ndev, &priv->rx.desc[entry], in ave_rxdesc_prepare()
610 skb->data - AVE_FRAME_HEADROOM, in ave_rxdesc_prepare()
618 priv->rx.desc[entry].skbs = skb; in ave_rxdesc_prepare()
639 writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC); in ave_desc_switch()
643 writel(0, priv->base + AVE_DESCC); in ave_desc_switch()
644 if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, in ave_desc_switch()
647 ret = -EBUSY; in ave_desc_switch()
652 val = readl(priv->base + AVE_DESCC); in ave_desc_switch()
655 writel(val, priv->base + AVE_DESCC); in ave_desc_switch()
656 if (readl_poll_timeout(priv->base + AVE_DESCC, val, in ave_desc_switch()
660 ret = -EBUSY; in ave_desc_switch()
665 val = readl(priv->base + AVE_DESCC); in ave_desc_switch()
668 writel(val, priv->base + AVE_DESCC); in ave_desc_switch()
672 ret = -EINVAL; in ave_desc_switch()
687 proc_idx = priv->tx.proc_idx; in ave_tx_complete()
688 done_idx = priv->tx.done_idx; in ave_tx_complete()
689 ndesc = priv->tx.ndesc; in ave_tx_complete()
691 /* free pre-stored skb from done_idx to proc_idx */ in ave_tx_complete()
695 /* do nothing if owner is HW (==1 for Tx) */ in ave_tx_complete()
699 /* check Tx status and updates statistics */ in ave_tx_complete()
708 priv->stats_tx.errors++; in ave_tx_complete()
710 priv->stats_tx.collisions++; in ave_tx_complete()
715 if (priv->tx.desc[done_idx].skbs) { in ave_tx_complete()
716 ave_dma_unmap(ndev, &priv->tx.desc[done_idx], in ave_tx_complete()
718 dev_consume_skb_any(priv->tx.desc[done_idx].skbs); in ave_tx_complete()
719 priv->tx.desc[done_idx].skbs = NULL; in ave_tx_complete()
725 priv->tx.done_idx = done_idx; in ave_tx_complete()
728 u64_stats_update_begin(&priv->stats_tx.syncp); in ave_tx_complete()
729 priv->stats_tx.packets += tx_packets; in ave_tx_complete()
730 priv->stats_tx.bytes += tx_bytes; in ave_tx_complete()
731 u64_stats_update_end(&priv->stats_tx.syncp); in ave_tx_complete()
751 proc_idx = priv->rx.proc_idx; in ave_rx_receive()
752 done_idx = priv->rx.done_idx; in ave_rx_receive()
753 ndesc = priv->rx.ndesc; in ave_rx_receive()
754 restpkt = ((proc_idx + ndesc - 1) - done_idx) % ndesc; in ave_rx_receive()
758 if (--restpkt < 0) in ave_rx_receive()
768 priv->stats_rx.errors++; in ave_rx_receive()
776 skb = priv->rx.desc[proc_idx].skbs; in ave_rx_receive()
777 priv->rx.desc[proc_idx].skbs = NULL; in ave_rx_receive()
779 ave_dma_unmap(ndev, &priv->rx.desc[proc_idx], DMA_FROM_DEVICE); in ave_rx_receive()
781 skb->dev = ndev; in ave_rx_receive()
783 skb->protocol = eth_type_trans(skb, ndev); in ave_rx_receive()
786 skb->ip_summed = CHECKSUM_UNNECESSARY; in ave_rx_receive()
796 priv->rx.proc_idx = proc_idx; in ave_rx_receive()
799 u64_stats_update_begin(&priv->stats_rx.syncp); in ave_rx_receive()
800 priv->stats_rx.packets += rx_packets; in ave_rx_receive()
801 priv->stats_rx.bytes += rx_bytes; in ave_rx_receive()
802 u64_stats_update_end(&priv->stats_rx.syncp); in ave_rx_receive()
811 priv->rx.done_idx = done_idx; in ave_rx_receive()
823 ndev = priv->ndev; in ave_napi_poll_rx()
843 ndev = priv->ndev; in ave_napi_poll_tx()
848 /* enable Tx interrupt when NAPI finishes */ in ave_napi_poll_tx()
861 if (!phy_interface_mode_is_rgmii(priv->phy_mode)) in ave_global_reset()
863 writel(val, priv->base + AVE_CFGR); in ave_global_reset()
866 val = readl(priv->base + AVE_RSTCTRL); in ave_global_reset()
868 writel(val, priv->base + AVE_RSTCTRL); in ave_global_reset()
871 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR); in ave_global_reset()
875 writel(AVE_GRR_GRST, priv->base + AVE_GRR); in ave_global_reset()
879 writel(0, priv->base + AVE_GRR); in ave_global_reset()
883 val = readl(priv->base + AVE_RSTCTRL); in ave_global_reset()
885 writel(val, priv->base + AVE_RSTCTRL); in ave_global_reset()
895 /* save and disable MAC receive op */ in ave_rxfifo_reset()
896 rxcr_org = readl(priv->base + AVE_RXCR); in ave_rxfifo_reset()
897 writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR); in ave_rxfifo_reset()
903 ave_rx_receive(ndev, priv->rx.ndesc); in ave_rxfifo_reset()
906 writel(AVE_GRR_RXFFR, priv->base + AVE_GRR); in ave_rxfifo_reset()
910 writel(0, priv->base + AVE_GRR); in ave_rxfifo_reset()
914 writel(AVE_GI_RXOVF, priv->base + AVE_GISR); in ave_rxfifo_reset()
919 /* restore MAC reccieve op */ in ave_rxfifo_reset()
920 writel(rxcr_org, priv->base + AVE_RXCR); in ave_rxfifo_reset()
932 gisr_val = readl(priv->base + AVE_GISR); in ave_irq_handler()
936 writel(AVE_GI_PHY, priv->base + AVE_GISR); in ave_irq_handler()
940 writel(AVE_GI_RXERR, priv->base + AVE_GISR); in ave_irq_handler()
950 priv->stats_rx.fifo_errors++; in ave_irq_handler()
957 priv->stats_rx.dropped++; in ave_irq_handler()
958 writel(AVE_GI_RXDROP, priv->base + AVE_GISR); in ave_irq_handler()
963 napi_schedule(&priv->napi_rx); in ave_irq_handler()
968 /* Tx completed */ in ave_irq_handler()
970 napi_schedule(&priv->napi_tx); in ave_irq_handler()
971 /* still force to disable Tx interrupt until NAPI finishes */ in ave_irq_handler()
987 return -EINVAL; in ave_pfsel_start()
989 val = readl(priv->base + AVE_PFEN); in ave_pfsel_start()
990 writel(val | BIT(entry), priv->base + AVE_PFEN); in ave_pfsel_start()
1001 return -EINVAL; in ave_pfsel_stop()
1003 val = readl(priv->base + AVE_PFEN); in ave_pfsel_stop()
1004 writel(val & ~BIT(entry), priv->base + AVE_PFEN); in ave_pfsel_stop()
1017 return -EINVAL; in ave_pfsel_set_macaddr()
1019 return -EINVAL; in ave_pfsel_set_macaddr()
1023 /* set MAC address for the filter */ in ave_pfsel_set_macaddr()
1029 priv->base + AVE_PFMBYTE(entry)); in ave_pfsel_set_macaddr()
1030 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); in ave_pfsel_set_macaddr()
1033 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); in ave_pfsel_set_macaddr()
1036 writel(0, priv->base + AVE_PFSEL(entry)); in ave_pfsel_set_macaddr()
1055 writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry)); in ave_pfsel_set_promisc()
1056 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); in ave_pfsel_set_promisc()
1059 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); in ave_pfsel_set_promisc()
1062 writel(rxring, priv->base + AVE_PFSEL(entry)); in ave_pfsel_set_promisc()
1081 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); in ave_pfsel_init()
1090 struct phy_device *phydev = ndev->phydev; in ave_phy_adjust_link()
1096 val = readl(priv->base + AVE_TXCR); in ave_phy_adjust_link()
1099 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) in ave_phy_adjust_link()
1101 else if (phydev->speed == SPEED_100) in ave_phy_adjust_link()
1104 writel(val, priv->base + AVE_TXCR); in ave_phy_adjust_link()
1108 val = readl(priv->base + AVE_LINKSEL); in ave_phy_adjust_link()
1109 if (phydev->speed == SPEED_10) in ave_phy_adjust_link()
1113 writel(val, priv->base + AVE_LINKSEL); in ave_phy_adjust_link()
1117 rxcr = readl(priv->base + AVE_RXCR); in ave_phy_adjust_link()
1118 txcr = readl(priv->base + AVE_TXCR); in ave_phy_adjust_link()
1121 if (phydev->duplex) { in ave_phy_adjust_link()
1124 if (phydev->pause) in ave_phy_adjust_link()
1126 if (phydev->asym_pause) in ave_phy_adjust_link()
1129 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); in ave_phy_adjust_link()
1146 /* disable Rx mac */ in ave_phy_adjust_link()
1147 writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR); in ave_phy_adjust_link()
1148 /* change and enable TX/Rx mac */ in ave_phy_adjust_link()
1149 writel(txcr, priv->base + AVE_TXCR); in ave_phy_adjust_link()
1150 writel(rxcr, priv->base + AVE_RXCR); in ave_phy_adjust_link()
1158 ave_hw_write_macaddr(ndev, ndev->dev_addr, AVE_RXMAC1R, AVE_RXMAC2R); in ave_macaddr_init()
1161 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6); in ave_macaddr_init()
1168 struct device *dev = ndev->dev.parent; in ave_init()
1169 struct device_node *np = dev->of_node; in ave_init()
1174 /* enable clk because of hw access until ndo_open */ in ave_init()
1175 for (nc = 0; nc < priv->nclks; nc++) { in ave_init()
1176 ret = clk_prepare_enable(priv->clk[nc]); in ave_init()
1183 for (nr = 0; nr < priv->nrsts; nr++) { in ave_init()
1184 ret = reset_control_deassert(priv->rst[nr]); in ave_init()
1191 ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, in ave_init()
1192 priv->pinmode_mask, priv->pinmode_val); in ave_init()
1201 ret = -EINVAL; in ave_init()
1204 ret = of_mdiobus_register(priv->mdio, mdio_np); in ave_init()
1214 ret = -ENODEV; in ave_init()
1218 priv->phydev = phydev; in ave_init()
1221 device_set_wakeup_capable(&ndev->dev, !!wol.supported); in ave_init()
1237 mdiobus_unregister(priv->mdio); in ave_init()
1239 while (--nr >= 0) in ave_init()
1240 reset_control_assert(priv->rst[nr]); in ave_init()
1242 while (--nc >= 0) in ave_init()
1243 clk_disable_unprepare(priv->clk[nc]); in ave_init()
1253 phy_disconnect(priv->phydev); in ave_uninit()
1254 mdiobus_unregister(priv->mdio); in ave_uninit()
1256 /* disable clk because of hw access after ndo_stop */ in ave_uninit()
1257 for (i = 0; i < priv->nrsts; i++) in ave_uninit()
1258 reset_control_assert(priv->rst[i]); in ave_uninit()
1259 for (i = 0; i < priv->nclks; i++) in ave_uninit()
1260 clk_disable_unprepare(priv->clk[i]); in ave_uninit()
1270 ret = request_irq(priv->irq, ave_irq_handler, IRQF_SHARED, ndev->name, in ave_open()
1275 priv->tx.desc = kcalloc(priv->tx.ndesc, sizeof(*priv->tx.desc), in ave_open()
1277 if (!priv->tx.desc) { in ave_open()
1278 ret = -ENOMEM; in ave_open()
1282 priv->rx.desc = kcalloc(priv->rx.ndesc, sizeof(*priv->rx.desc), in ave_open()
1284 if (!priv->rx.desc) { in ave_open()
1285 kfree(priv->tx.desc); in ave_open()
1286 ret = -ENOMEM; in ave_open()
1290 /* initialize Tx work and descriptor */ in ave_open()
1291 priv->tx.proc_idx = 0; in ave_open()
1292 priv->tx.done_idx = 0; in ave_open()
1293 for (entry = 0; entry < priv->tx.ndesc; entry++) { in ave_open()
1298 (((priv->tx.ndesc * priv->desc_size) << 16) & AVE_TXDC_SIZE), in ave_open()
1299 priv->base + AVE_TXDC); in ave_open()
1302 priv->rx.proc_idx = 0; in ave_open()
1303 priv->rx.done_idx = 0; in ave_open()
1304 for (entry = 0; entry < priv->rx.ndesc; entry++) { in ave_open()
1309 (((priv->rx.ndesc * priv->desc_size) << 16) & AVE_RXDC0_SIZE), in ave_open()
1310 priv->base + AVE_RXDC0); in ave_open()
1321 writel(val, priv->base + AVE_RXCR); in ave_open()
1323 /* set Tx configuration */ in ave_open()
1325 writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR); in ave_open()
1328 val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; in ave_open()
1330 writel(val, priv->base + AVE_IIRQC); in ave_open()
1335 napi_enable(&priv->napi_rx); in ave_open()
1336 napi_enable(&priv->napi_tx); in ave_open()
1338 phy_start(ndev->phydev); in ave_open()
1339 phy_start_aneg(ndev->phydev); in ave_open()
1345 disable_irq(priv->irq); in ave_open()
1346 free_irq(priv->irq, ndev); in ave_open()
1357 disable_irq(priv->irq); in ave_stop()
1358 free_irq(priv->irq, ndev); in ave_stop()
1361 phy_stop(ndev->phydev); in ave_stop()
1362 napi_disable(&priv->napi_tx); in ave_stop()
1363 napi_disable(&priv->napi_rx); in ave_stop()
1367 /* free Tx buffer */ in ave_stop()
1368 for (entry = 0; entry < priv->tx.ndesc; entry++) { in ave_stop()
1369 if (!priv->tx.desc[entry].skbs) in ave_stop()
1372 ave_dma_unmap(ndev, &priv->tx.desc[entry], DMA_TO_DEVICE); in ave_stop()
1373 dev_kfree_skb_any(priv->tx.desc[entry].skbs); in ave_stop()
1374 priv->tx.desc[entry].skbs = NULL; in ave_stop()
1376 priv->tx.proc_idx = 0; in ave_stop()
1377 priv->tx.done_idx = 0; in ave_stop()
1380 for (entry = 0; entry < priv->rx.ndesc; entry++) { in ave_stop()
1381 if (!priv->rx.desc[entry].skbs) in ave_stop()
1384 ave_dma_unmap(ndev, &priv->rx.desc[entry], DMA_FROM_DEVICE); in ave_stop()
1385 dev_kfree_skb_any(priv->rx.desc[entry].skbs); in ave_stop()
1386 priv->rx.desc[entry].skbs = NULL; in ave_stop()
1388 priv->rx.proc_idx = 0; in ave_stop()
1389 priv->rx.done_idx = 0; in ave_stop()
1391 kfree(priv->tx.desc); in ave_stop()
1392 kfree(priv->rx.desc); in ave_stop()
1404 proc_idx = priv->tx.proc_idx; in ave_start_xmit()
1405 done_idx = priv->tx.done_idx; in ave_start_xmit()
1406 ndesc = priv->tx.ndesc; in ave_start_xmit()
1407 freepkt = ((done_idx + ndesc - 1) - proc_idx) % ndesc; in ave_start_xmit()
1417 priv->stats_tx.dropped++; in ave_start_xmit()
1421 /* map Tx buffer in ave_start_xmit()
1422 * Tx buffer set to the Tx descriptor doesn't have any restriction. in ave_start_xmit()
1424 ret = ave_dma_map(ndev, &priv->tx.desc[proc_idx], in ave_start_xmit()
1425 skb->data, skb->len, DMA_TO_DEVICE, &paddr); in ave_start_xmit()
1428 priv->stats_tx.dropped++; in ave_start_xmit()
1432 priv->tx.desc[proc_idx].skbs = skb; in ave_start_xmit()
1437 (skb->len & AVE_STS_PKTLEN_TX_MASK); in ave_start_xmit()
1444 if (skb->ip_summed == CHECKSUM_NONE || in ave_start_xmit()
1445 skb->ip_summed == CHECKSUM_UNNECESSARY) in ave_start_xmit()
1450 priv->tx.proc_idx = (proc_idx + 1) % ndesc; in ave_start_xmit()
1457 return phy_mii_ioctl(ndev->phydev, ifr, cmd); in ave_ioctl()
1470 /* MAC addr filter enable for promiscious mode */ in ave_set_rx_mode()
1472 val = readl(priv->base + AVE_RXCR); in ave_set_rx_mode()
1473 if (ndev->flags & IFF_PROMISC || !mc_cnt) in ave_set_rx_mode()
1477 writel(val, priv->base + AVE_RXCR); in ave_set_rx_mode()
1480 if ((ndev->flags & IFF_ALLMULTI) || mc_cnt > AVE_PF_MULTICAST_SIZE) { in ave_set_rx_mode()
1496 hw_adr->addr, 6); in ave_set_rx_mode()
1509 start = u64_stats_fetch_begin_irq(&priv->stats_rx.syncp); in ave_get_stats64()
1510 stats->rx_packets = priv->stats_rx.packets; in ave_get_stats64()
1511 stats->rx_bytes = priv->stats_rx.bytes; in ave_get_stats64()
1512 } while (u64_stats_fetch_retry_irq(&priv->stats_rx.syncp, start)); in ave_get_stats64()
1515 start = u64_stats_fetch_begin_irq(&priv->stats_tx.syncp); in ave_get_stats64()
1516 stats->tx_packets = priv->stats_tx.packets; in ave_get_stats64()
1517 stats->tx_bytes = priv->stats_tx.bytes; in ave_get_stats64()
1518 } while (u64_stats_fetch_retry_irq(&priv->stats_tx.syncp, start)); in ave_get_stats64()
1520 stats->rx_errors = priv->stats_rx.errors; in ave_get_stats64()
1521 stats->tx_errors = priv->stats_tx.errors; in ave_get_stats64()
1522 stats->rx_dropped = priv->stats_rx.dropped; in ave_get_stats64()
1523 stats->tx_dropped = priv->stats_tx.dropped; in ave_get_stats64()
1524 stats->rx_fifo_errors = priv->stats_rx.fifo_errors; in ave_get_stats64()
1525 stats->collisions = priv->stats_tx.collisions; in ave_get_stats64()
1555 struct device *dev = &pdev->dev; in ave_probe()
1571 return -EINVAL; in ave_probe()
1573 np = dev->of_node; in ave_probe()
1576 dev_err(dev, "phy-mode not found\n"); in ave_probe()
1591 return -ENOMEM; in ave_probe()
1594 ndev->netdev_ops = &ave_netdev_ops; in ave_probe()
1595 ndev->ethtool_ops = &ave_ethtool_ops; in ave_probe()
1598 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); in ave_probe()
1599 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM); in ave_probe()
1601 ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN); in ave_probe()
1605 ether_addr_copy(ndev->dev_addr, mac_addr); in ave_probe()
1607 /* if the mac address is invalid, use random mac address */ in ave_probe()
1608 if (!is_valid_ether_addr(ndev->dev_addr)) { in ave_probe()
1610 dev_warn(dev, "Using random MAC address: %pM\n", in ave_probe()
1611 ndev->dev_addr); in ave_probe()
1615 priv->base = base; in ave_probe()
1616 priv->irq = irq; in ave_probe()
1617 priv->ndev = ndev; in ave_probe()
1618 priv->msg_enable = netif_msg_init(-1, AVE_DEFAULT_MSG_ENABLE); in ave_probe()
1619 priv->phy_mode = phy_mode; in ave_probe()
1620 priv->data = data; in ave_probe()
1623 priv->desc_size = AVE_DESC_SIZE_64; in ave_probe()
1624 priv->tx.daddr = AVE_TXDM_64; in ave_probe()
1625 priv->rx.daddr = AVE_RXDM_64; in ave_probe()
1628 priv->desc_size = AVE_DESC_SIZE_32; in ave_probe()
1629 priv->tx.daddr = AVE_TXDM_32; in ave_probe()
1630 priv->rx.daddr = AVE_RXDM_32; in ave_probe()
1637 priv->tx.ndesc = AVE_NR_TXDESC; in ave_probe()
1638 priv->rx.ndesc = AVE_NR_RXDESC; in ave_probe()
1640 u64_stats_init(&priv->stats_tx.syncp); in ave_probe()
1641 u64_stats_init(&priv->stats_rx.syncp); in ave_probe()
1644 name = priv->data->clock_names[i]; in ave_probe()
1647 priv->clk[i] = devm_clk_get(dev, name); in ave_probe()
1648 if (IS_ERR(priv->clk[i])) in ave_probe()
1649 return PTR_ERR(priv->clk[i]); in ave_probe()
1650 priv->nclks++; in ave_probe()
1654 name = priv->data->reset_names[i]; in ave_probe()
1657 priv->rst[i] = devm_reset_control_get_shared(dev, name); in ave_probe()
1658 if (IS_ERR(priv->rst[i])) in ave_probe()
1659 return PTR_ERR(priv->rst[i]); in ave_probe()
1660 priv->nrsts++; in ave_probe()
1664 "socionext,syscon-phy-mode", in ave_probe()
1667 dev_err(dev, "can't get syscon-phy-mode property\n"); in ave_probe()
1670 priv->regmap = syscon_node_to_regmap(args.np); in ave_probe()
1672 if (IS_ERR(priv->regmap)) { in ave_probe()
1673 dev_err(dev, "can't map syscon-phy-mode\n"); in ave_probe()
1674 return PTR_ERR(priv->regmap); in ave_probe()
1676 ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); in ave_probe()
1678 dev_err(dev, "invalid phy-mode setting\n"); in ave_probe()
1682 priv->mdio = devm_mdiobus_alloc(dev); in ave_probe()
1683 if (!priv->mdio) in ave_probe()
1684 return -ENOMEM; in ave_probe()
1685 priv->mdio->priv = ndev; in ave_probe()
1686 priv->mdio->parent = dev; in ave_probe()
1687 priv->mdio->read = ave_mdiobus_read; in ave_probe()
1688 priv->mdio->write = ave_mdiobus_write; in ave_probe()
1689 priv->mdio->name = "uniphier-mdio"; in ave_probe()
1690 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%x", in ave_probe()
1691 pdev->name, pdev->id); in ave_probe()
1694 netif_napi_add(ndev, &priv->napi_rx, ave_napi_poll_rx, in ave_probe()
1696 netif_tx_napi_add(ndev, &priv->napi_tx, ave_napi_poll_tx, in ave_probe()
1708 ave_id = readl(priv->base + AVE_IDR); in ave_probe()
1714 buf, priv->irq, phy_modes(phy_mode)); in ave_probe()
1719 netif_napi_del(&priv->napi_rx); in ave_probe()
1720 netif_napi_del(&priv->napi_tx); in ave_probe()
1731 netif_napi_del(&priv->napi_rx); in ave_remove()
1732 netif_napi_del(&priv->napi_tx); in ave_remove()
1751 priv->wolopts = wol.wolopts; in ave_suspend()
1766 wol.wolopts = priv->wolopts; in ave_resume()
1769 if (ndev->phydev) { in ave_resume()
1770 ret = phy_resume(ndev->phydev); in ave_resume()
1793 return -EINVAL; in ave_pro4_get_pinmode()
1795 priv->pinmode_mask = SG_ETPINMODE_RMII(0); in ave_pro4_get_pinmode()
1799 priv->pinmode_val = SG_ETPINMODE_RMII(0); in ave_pro4_get_pinmode()
1806 priv->pinmode_val = 0; in ave_pro4_get_pinmode()
1809 return -EINVAL; in ave_pro4_get_pinmode()
1819 return -EINVAL; in ave_ld11_get_pinmode()
1821 priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); in ave_ld11_get_pinmode()
1825 priv->pinmode_val = 0; in ave_ld11_get_pinmode()
1828 priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); in ave_ld11_get_pinmode()
1831 return -EINVAL; in ave_ld11_get_pinmode()
1841 return -EINVAL; in ave_ld20_get_pinmode()
1843 priv->pinmode_mask = SG_ETPINMODE_RMII(0); in ave_ld20_get_pinmode()
1847 priv->pinmode_val = SG_ETPINMODE_RMII(0); in ave_ld20_get_pinmode()
1853 priv->pinmode_val = 0; in ave_ld20_get_pinmode()
1856 return -EINVAL; in ave_ld20_get_pinmode()
1866 return -EINVAL; in ave_pxs3_get_pinmode()
1868 priv->pinmode_mask = SG_ETPINMODE_RMII(arg); in ave_pxs3_get_pinmode()
1872 priv->pinmode_val = SG_ETPINMODE_RMII(arg); in ave_pxs3_get_pinmode()
1878 priv->pinmode_val = 0; in ave_pxs3_get_pinmode()
1881 return -EINVAL; in ave_pxs3_get_pinmode()
1890 "gio", "ether", "ether-gb", "ether-phy",
1944 .compatible = "socionext,uniphier-pro4-ave4",
1948 .compatible = "socionext,uniphier-pxs2-ave4",
1952 .compatible = "socionext,uniphier-ld11-ave4",
1956 .compatible = "socionext,uniphier-ld20-ave4",
1960 .compatible = "socionext,uniphier-pxs3-ave4",