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/linux/sound/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Tegra" menu
5 tristate "SoC Audio for the Tegra System-on-Chip"
12 Say Y or M here if you want support for SoC audio on Tegra.
85 Config to enable the Inter-IC Sound (I2S) Controller which
86 implements full-duplex and bidirectional and single direction
87 point-to-point serial interfaces. It can interface with I2S
116 converts the multi-bit Pulse Code Modulation (PCM) audio input to
117 oversampled 1-bit Pulse Density Modulation (PDM) output. From the
119 that up-samples the input to the desired sampling rate by
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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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H A Dnvidia,nvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,nvec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
26 - description: divider clock
27 - description: fast clock
29 clock-names:
32 - const: div-clk
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/linux/drivers/staging/nvec/
H A DREADME4 embedded controller (EC) via I2C bus. The EC is an I2C master while the host
5 processor is the I2C slave. Requests from the host processor to the EC are
11 that other Tegra boards (not yet mainlined, if ever) also use it.
13 [1] e.g. https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=tree;f=arch/arm/mach-tegra/nvec;hb=a…
/linux/drivers/i2c/busses/
H A Di2c-tegra-bpmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/i2c/busses/i2c-tegra-bpmp.c
11 #include <linux/i2c.h>
19 #include <soc/tegra/bpmp-abi.h>
20 #include <soc/tegra/bpmp.h>
23 * Serialized I2C message header size is 6 bytes and includes address, flags
37 * Linux flags are translated to BPMP defined I2C flags that are used in BPMP
38 * firmware I2C driver to avoid any issues in future if Linux I2C flags are
69 * The serialized I2C format is simply the following:
70 * [addr little-endian][flags little-endian][len little-endian][data if write]
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the i2c bus drivers.
7 obj-$(CONFIG_I2C_SCMI) += i2c-scmi.o
9 # Auxiliary I2C/SMBus modules
10 obj-$(CONFIG_I2C_CCGX_UCSI) += i2c-ccgx-ucsi.o
13 obj-$(CONFIG_I2C_ALI1535) += i2c-ali1535.o
14 obj-$(CONFIG_I2C_ALI1563) += i2c-ali1563.o
15 obj-$(CONFIG_I2C_ALI15X3) += i2c-ali15x3.o
16 obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o
17 obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra DisplayPort AUX Interface
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
15 pins which can be assigned to either the DPAUX channel or to an I2C
24 pattern: "^dpaux@[0-9a-f]+$"
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H A Dnvidia,tegra20-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra HDMI Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^hdmi@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-hdmi
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H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Serial Interface
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
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H A Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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H A Dnvidia,tegra20-vi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Input controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^vi@[0-9a-f]+$"
19 - const: nvidia,tegra20-vi
20 - const: nvidia,tegra30-vi
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/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dos.h1 /* SPDX-License-Identifier: MIT */
14 #include <linux/i2c.h>
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
15 rtc0 = "/i2c@7000d000/tps6586x@34";
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
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H A Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
7 i2c@7000d000 {
13 #interrupt-cells = <2>;
14 interrupt-controller;
15 wakeup-source;
17 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
18 ti,system-power-controller;
19 ti,sleep-keep-ck32k;
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H A Dtegra30-asus-nexus7-grouper-maxim-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/mfd/max77620.h>
8 i2c@7000d000 {
14 #interrupt-cells = <2>;
15 interrupt-controller;
17 #gpio-cells = <2>;
18 gpio-controller;
20 system-power-controller;
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H A Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
26 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
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H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
18 rtc0 = "/i2c@7000d000/tps6586x@34";
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
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H A Dtegra20-tec.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
16 i2c@7000c000 {
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
28 gpio-cfg = <0xffffffff
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H A Dtegra20-plutux.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
16 i2c@7000c000 {
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
28 gpio-cfg = <0xffffffff
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H A Dtegra20-medcom-wide.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
7 model = "Avionic Design Medcom-Wide board";
8 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
15 stdout-path = "serial0:115200n8";
31 i2c@7000c000 {
35 interrupt-parent = <&gpio>;
38 gpio-controller;
39 #gpio-cells = <2>;
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/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The BPMP is a specific processor in Tegra chip, which is designed for
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
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/linux/drivers/clk/tegra/
H A Dclk-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
15 #include <dt-bindings/clock/tegra20-car.h>
18 #include "clk-id.h"
113 /* Tegra CPU clock and reset control regs */
444 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
445 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
446 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
448 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
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H A Dclk-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
16 #include <soc/tegra/pmc.h>
18 #include <dt-bindings/clock/tegra30-car.h>
21 #include "clk-id.h"
112 /* Tegra CPU clock and reset control regs */
595 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
596 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
597 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
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/linux/Documentation/devicetree/
H A Dusage-model.rst1 .. SPDX-License-Identifier: GPL-2.0
39 incompatible, bindings for i2c busses that came about because the new
40 binding was created without first investigating how i2c devices were
44 ----------
56 In 2005, when PowerPC Linux began a major cleanup and to merge 32-bit
57 and 64-bit support, the decision was made to require DT support on all
61 blob without requiring a real Open Firmware implementation. U-Boot,
66 existing non-DT aware firmware.
74 -------------
79 -------------------
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/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
120 cores. This bus is for per-CPU tightly coupled devices such as the
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