xref: /linux/arch/arm/boot/dts/nvidia/tegra20-ventana.dts (revision a23e1966932464e1c5226cb9ac4ce1d5fc10ba22)
1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0
2add29e61SPeter De Schrijver/dts-v1/;
3add29e61SPeter De Schrijver
46bccbd5eSLaxman Dewangan#include <dt-bindings/input/input.h>
53744c7d8SDmitry Osipenko#include <dt-bindings/thermal/thermal.h>
61bd0bd49SStephen Warren#include "tegra20.dtsi"
7bd7cd7e0SJon Hunter#include "tegra20-cpu-opp.dtsi"
882d3d459SDmitry Osipenko#include "tegra20-cpu-opp-microvolt.dtsi"
9add29e61SPeter De Schrijver
10add29e61SPeter De Schrijver/ {
118fef5dffSBryan Wu	model = "NVIDIA Tegra20 Ventana evaluation board";
12add29e61SPeter De Schrijver	compatible = "nvidia,ventana", "nvidia,tegra20";
13add29e61SPeter De Schrijver
14553c0a20SStephen Warren	aliases {
15553c0a20SStephen Warren		rtc0 = "/i2c@7000d000/tps6586x@34";
16553c0a20SStephen Warren		rtc1 = "/rtc@7000e000";
17c4574aa0SOlof Johansson		serial0 = &uartd;
18553c0a20SStephen Warren	};
19553c0a20SStephen Warren
20f5bbb327SJon Hunter	chosen {
21f5bbb327SJon Hunter		stdout-path = "serial0:115200n8";
22f5bbb327SJon Hunter	};
23f5bbb327SJon Hunter
2448299769SKrzysztof Kozlowski	memory@0 {
25add29e61SPeter De Schrijver		reg = <0x00000000 0x40000000>;
26add29e61SPeter De Schrijver	};
27add29e61SPeter De Schrijver
2858ecb23fSStephen Warren	host1x@50000000 {
291771a254SStephen Warren		dc@54200000 {
301771a254SStephen Warren			rgb {
311771a254SStephen Warren				status = "okay";
321771a254SStephen Warren
331771a254SStephen Warren				nvidia,panel = <&panel>;
341771a254SStephen Warren			};
351771a254SStephen Warren		};
361771a254SStephen Warren
3758ecb23fSStephen Warren		hdmi@54280000 {
3897d5520fSStephen Warren			status = "okay";
3997d5520fSStephen Warren
4097d5520fSStephen Warren			vdd-supply = <&hdmi_vdd_reg>;
4197d5520fSStephen Warren			pll-supply = <&hdmi_pll_reg>;
4297d5520fSStephen Warren
4397d5520fSStephen Warren			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
443325f1bcSStephen Warren			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
453325f1bcSStephen Warren				GPIO_ACTIVE_HIGH>;
4697d5520fSStephen Warren		};
4797d5520fSStephen Warren	};
4897d5520fSStephen Warren
4958ecb23fSStephen Warren	pinmux@70000014 {
50ecc295bbSStephen Warren		pinctrl-names = "default";
51ecc295bbSStephen Warren		pinctrl-0 = <&state_default>;
52ecc295bbSStephen Warren
53ecc295bbSStephen Warren		state_default: pinmux {
54ecc295bbSStephen Warren			ata {
55ecc295bbSStephen Warren				nvidia,pins = "ata";
56ecc295bbSStephen Warren				nvidia,function = "ide";
57ecc295bbSStephen Warren			};
58ecc295bbSStephen Warren			atb {
59ecc295bbSStephen Warren				nvidia,pins = "atb", "gma", "gme";
60ecc295bbSStephen Warren				nvidia,function = "sdio4";
61ecc295bbSStephen Warren			};
62ecc295bbSStephen Warren			atc {
63ecc295bbSStephen Warren				nvidia,pins = "atc";
64ecc295bbSStephen Warren				nvidia,function = "nand";
65ecc295bbSStephen Warren			};
66ecc295bbSStephen Warren			atd {
67ecc295bbSStephen Warren				nvidia,pins = "atd", "ate", "gmb", "spia",
68ecc295bbSStephen Warren					"spib", "spic";
69ecc295bbSStephen Warren				nvidia,function = "gmi";
70ecc295bbSStephen Warren			};
71ecc295bbSStephen Warren			cdev1 {
72ecc295bbSStephen Warren				nvidia,pins = "cdev1";
73ecc295bbSStephen Warren				nvidia,function = "plla_out";
74ecc295bbSStephen Warren			};
75ecc295bbSStephen Warren			cdev2 {
76ecc295bbSStephen Warren				nvidia,pins = "cdev2";
77ecc295bbSStephen Warren				nvidia,function = "pllp_out4";
78ecc295bbSStephen Warren			};
79ecc295bbSStephen Warren			crtp {
80ecc295bbSStephen Warren				nvidia,pins = "crtp", "lm1";
81ecc295bbSStephen Warren				nvidia,function = "crt";
82ecc295bbSStephen Warren			};
83ecc295bbSStephen Warren			csus {
84ecc295bbSStephen Warren				nvidia,pins = "csus";
85ecc295bbSStephen Warren				nvidia,function = "vi_sensor_clk";
86ecc295bbSStephen Warren			};
87ecc295bbSStephen Warren			dap1 {
88ecc295bbSStephen Warren				nvidia,pins = "dap1";
89ecc295bbSStephen Warren				nvidia,function = "dap1";
90ecc295bbSStephen Warren			};
91ecc295bbSStephen Warren			dap2 {
92ecc295bbSStephen Warren				nvidia,pins = "dap2";
93ecc295bbSStephen Warren				nvidia,function = "dap2";
94ecc295bbSStephen Warren			};
95ecc295bbSStephen Warren			dap3 {
96ecc295bbSStephen Warren				nvidia,pins = "dap3";
97ecc295bbSStephen Warren				nvidia,function = "dap3";
98ecc295bbSStephen Warren			};
99ecc295bbSStephen Warren			dap4 {
100ecc295bbSStephen Warren				nvidia,pins = "dap4";
101ecc295bbSStephen Warren				nvidia,function = "dap4";
102ecc295bbSStephen Warren			};
103ecc295bbSStephen Warren			dta {
104ecc295bbSStephen Warren				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
105ecc295bbSStephen Warren				nvidia,function = "vi";
106ecc295bbSStephen Warren			};
107ecc295bbSStephen Warren			dtf {
108ecc295bbSStephen Warren				nvidia,pins = "dtf";
109ecc295bbSStephen Warren				nvidia,function = "i2c3";
110ecc295bbSStephen Warren			};
111ecc295bbSStephen Warren			gmc {
112ecc295bbSStephen Warren				nvidia,pins = "gmc";
113ecc295bbSStephen Warren				nvidia,function = "uartd";
114ecc295bbSStephen Warren			};
115ecc295bbSStephen Warren			gmd {
116ecc295bbSStephen Warren				nvidia,pins = "gmd";
117ecc295bbSStephen Warren				nvidia,function = "sflash";
118ecc295bbSStephen Warren			};
119ecc295bbSStephen Warren			gpu {
120ecc295bbSStephen Warren				nvidia,pins = "gpu";
121ecc295bbSStephen Warren				nvidia,function = "pwm";
122ecc295bbSStephen Warren			};
123ecc295bbSStephen Warren			gpu7 {
124ecc295bbSStephen Warren				nvidia,pins = "gpu7";
125ecc295bbSStephen Warren				nvidia,function = "rtck";
126ecc295bbSStephen Warren			};
127ecc295bbSStephen Warren			gpv {
128ecc295bbSStephen Warren				nvidia,pins = "gpv", "slxa", "slxk";
129ecc295bbSStephen Warren				nvidia,function = "pcie";
130ecc295bbSStephen Warren			};
131ecc295bbSStephen Warren			hdint {
132cf633464SMark Zhang				nvidia,pins = "hdint";
133ecc295bbSStephen Warren				nvidia,function = "hdmi";
134ecc295bbSStephen Warren			};
135ecc295bbSStephen Warren			i2cp {
136ecc295bbSStephen Warren				nvidia,pins = "i2cp";
137ecc295bbSStephen Warren				nvidia,function = "i2cp";
138ecc295bbSStephen Warren			};
139ecc295bbSStephen Warren			irrx {
140ecc295bbSStephen Warren				nvidia,pins = "irrx", "irtx";
141ecc295bbSStephen Warren				nvidia,function = "uartb";
142ecc295bbSStephen Warren			};
143ecc295bbSStephen Warren			kbca {
144ecc295bbSStephen Warren				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
145ecc295bbSStephen Warren					"kbce", "kbcf";
146ecc295bbSStephen Warren				nvidia,function = "kbc";
147ecc295bbSStephen Warren			};
148ecc295bbSStephen Warren			lcsn {
149ecc295bbSStephen Warren				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
150ecc295bbSStephen Warren					"lsdi", "lvp0";
151ecc295bbSStephen Warren				nvidia,function = "rsvd4";
152ecc295bbSStephen Warren			};
153ecc295bbSStephen Warren			ld0 {
154ecc295bbSStephen Warren				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
155ecc295bbSStephen Warren					"ld5", "ld6", "ld7", "ld8", "ld9",
156ecc295bbSStephen Warren					"ld10", "ld11", "ld12", "ld13", "ld14",
157ecc295bbSStephen Warren					"ld15", "ld16", "ld17", "ldi", "lhp0",
158ecc295bbSStephen Warren					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
159ecc295bbSStephen Warren					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
160ecc295bbSStephen Warren					"lspi", "lvp1", "lvs";
161ecc295bbSStephen Warren				nvidia,function = "displaya";
162ecc295bbSStephen Warren			};
163cf633464SMark Zhang			owc {
164cf633464SMark Zhang				nvidia,pins = "owc", "spdi", "spdo", "uac";
165cf633464SMark Zhang				nvidia,function = "rsvd2";
166cf633464SMark Zhang			};
167ecc295bbSStephen Warren			pmc {
168ecc295bbSStephen Warren				nvidia,pins = "pmc";
169ecc295bbSStephen Warren				nvidia,function = "pwr_on";
170ecc295bbSStephen Warren			};
171ecc295bbSStephen Warren			rm {
172ecc295bbSStephen Warren				nvidia,pins = "rm";
173ecc295bbSStephen Warren				nvidia,function = "i2c1";
174ecc295bbSStephen Warren			};
175ecc295bbSStephen Warren			sdb {
176ecc295bbSStephen Warren				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
177ecc295bbSStephen Warren				nvidia,function = "sdio3";
178ecc295bbSStephen Warren			};
179ecc295bbSStephen Warren			sdio1 {
180ecc295bbSStephen Warren				nvidia,pins = "sdio1";
181ecc295bbSStephen Warren				nvidia,function = "sdio1";
182ecc295bbSStephen Warren			};
183ecc295bbSStephen Warren			slxd {
184ecc295bbSStephen Warren				nvidia,pins = "slxd";
185ecc295bbSStephen Warren				nvidia,function = "spdif";
186ecc295bbSStephen Warren			};
187ecc295bbSStephen Warren			spid {
188ecc295bbSStephen Warren				nvidia,pins = "spid", "spie", "spif";
189ecc295bbSStephen Warren				nvidia,function = "spi1";
190ecc295bbSStephen Warren			};
191ecc295bbSStephen Warren			spig {
192ecc295bbSStephen Warren				nvidia,pins = "spig", "spih";
193ecc295bbSStephen Warren				nvidia,function = "spi2_alt";
194ecc295bbSStephen Warren			};
195ecc295bbSStephen Warren			uaa {
196ecc295bbSStephen Warren				nvidia,pins = "uaa", "uab", "uda";
197ecc295bbSStephen Warren				nvidia,function = "ulpi";
198ecc295bbSStephen Warren			};
199ecc295bbSStephen Warren			uad {
200ecc295bbSStephen Warren				nvidia,pins = "uad";
201ecc295bbSStephen Warren				nvidia,function = "irda";
202ecc295bbSStephen Warren			};
203ecc295bbSStephen Warren			uca {
204ecc295bbSStephen Warren				nvidia,pins = "uca", "ucb";
205ecc295bbSStephen Warren				nvidia,function = "uartc";
206ecc295bbSStephen Warren			};
207ecc295bbSStephen Warren			conf_ata {
208ecc295bbSStephen Warren				nvidia,pins = "ata", "atb", "atc", "atd",
209ecc295bbSStephen Warren					"cdev1", "cdev2", "dap1", "dap2",
210ecc295bbSStephen Warren					"dap4", "ddc", "dtf", "gma", "gmc",
211ecc295bbSStephen Warren					"gme", "gpu", "gpu7", "i2cp", "irrx",
212ecc295bbSStephen Warren					"irtx", "pta", "rm", "sdc", "sdd",
213ecc295bbSStephen Warren					"slxc", "slxd", "slxk", "spdi", "spdo",
214ecc295bbSStephen Warren					"uac", "uad", "uca", "ucb", "uda";
215ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_DISABLE>;
217ecc295bbSStephen Warren			};
218ecc295bbSStephen Warren			conf_ate {
219ecc295bbSStephen Warren				nvidia,pins = "ate", "csus", "dap3", "gmd",
220ecc295bbSStephen Warren					"gpv", "owc", "spia", "spib", "spic",
221ecc295bbSStephen Warren					"spid", "spie", "spig";
222ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_ENABLE>;
224ecc295bbSStephen Warren			};
225ecc295bbSStephen Warren			conf_ck32 {
226ecc295bbSStephen Warren				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
227ecc295bbSStephen Warren					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
228ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
229ecc295bbSStephen Warren			};
230ecc295bbSStephen Warren			conf_crtp {
231ecc295bbSStephen Warren				nvidia,pins = "crtp", "gmb", "slxa", "spih";
232ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_UP>;
233ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_ENABLE>;
234ecc295bbSStephen Warren			};
235ecc295bbSStephen Warren			conf_dta {
236ecc295bbSStephen Warren				nvidia,pins = "dta", "dtb", "dtc", "dtd";
237ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_DISABLE>;
239ecc295bbSStephen Warren			};
240ecc295bbSStephen Warren			conf_dte {
241ecc295bbSStephen Warren				nvidia,pins = "dte", "spif";
242ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
243ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_ENABLE>;
244ecc295bbSStephen Warren			};
245ecc295bbSStephen Warren			conf_hdint {
246ecc295bbSStephen Warren				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
247ecc295bbSStephen Warren					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
248ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_ENABLE>;
249ecc295bbSStephen Warren			};
250ecc295bbSStephen Warren			conf_kbca {
251ecc295bbSStephen Warren				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
252ecc295bbSStephen Warren					"kbce", "kbcf", "sdio1", "uaa", "uab";
253ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_UP>;
254ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_DISABLE>;
255ecc295bbSStephen Warren			};
256ecc295bbSStephen Warren			conf_lc {
257ecc295bbSStephen Warren				nvidia,pins = "lc", "ls";
258ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_UP>;
259ecc295bbSStephen Warren			};
260ecc295bbSStephen Warren			conf_ld0 {
261ecc295bbSStephen Warren				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
262ecc295bbSStephen Warren					"ld5", "ld6", "ld7", "ld8", "ld9",
263ecc295bbSStephen Warren					"ld10", "ld11", "ld12", "ld13", "ld14",
264ecc295bbSStephen Warren					"ld15", "ld16", "ld17", "ldi", "lhp0",
265ecc295bbSStephen Warren					"lhp1", "lhp2", "lhs", "lm0", "lpp",
266ecc295bbSStephen Warren					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
267ecc295bbSStephen Warren					"lvp1", "lvs", "pmc", "sdb";
268ba4104e7SLaxman Dewangan				nvidia,tristate = <TEGRA_PIN_DISABLE>;
269ecc295bbSStephen Warren			};
270ecc295bbSStephen Warren			conf_ld17_0 {
271ecc295bbSStephen Warren				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
272ecc295bbSStephen Warren					"ld23_22";
273ba4104e7SLaxman Dewangan				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
274ecc295bbSStephen Warren			};
275c729429eSWei Ni			drive_sdio1 {
276c729429eSWei Ni				nvidia,pins = "drive_sdio1";
277ba4104e7SLaxman Dewangan				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
278ba4104e7SLaxman Dewangan				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
279ba4104e7SLaxman Dewangan				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
280c729429eSWei Ni				nvidia,pull-down-strength = <31>;
281c729429eSWei Ni				nvidia,pull-up-strength = <31>;
282ba4104e7SLaxman Dewangan				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
283ba4104e7SLaxman Dewangan				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
284c729429eSWei Ni			};
285ecc295bbSStephen Warren		};
286cf633464SMark Zhang
2871ca3b45eSThierry Reding		state_i2cmux_ddc: pinmux-i2cmux-ddc {
288cf633464SMark Zhang			ddc {
289cf633464SMark Zhang				nvidia,pins = "ddc";
290cf633464SMark Zhang				nvidia,function = "i2c2";
291cf633464SMark Zhang			};
292cf633464SMark Zhang			pta {
293cf633464SMark Zhang				nvidia,pins = "pta";
294cf633464SMark Zhang				nvidia,function = "rsvd4";
295cf633464SMark Zhang			};
296cf633464SMark Zhang		};
297cf633464SMark Zhang
2981ca3b45eSThierry Reding		state_i2cmux_idle: pinmux-i2cmux-idle {
299cf633464SMark Zhang			ddc {
300cf633464SMark Zhang				nvidia,pins = "ddc";
301cf633464SMark Zhang				nvidia,function = "rsvd4";
302cf633464SMark Zhang			};
303cf633464SMark Zhang			pta {
304cf633464SMark Zhang				nvidia,pins = "pta";
305cf633464SMark Zhang				nvidia,function = "rsvd4";
306cf633464SMark Zhang			};
307cf633464SMark Zhang		};
308d1e34a8aSThierry Reding
309d1e34a8aSThierry Reding		state_i2cmux_pta: pinmux-i2cmux-pta {
310d1e34a8aSThierry Reding			ddc {
311d1e34a8aSThierry Reding				nvidia,pins = "ddc";
312d1e34a8aSThierry Reding				nvidia,function = "rsvd4";
313d1e34a8aSThierry Reding			};
314d1e34a8aSThierry Reding			pta {
315d1e34a8aSThierry Reding				nvidia,pins = "pta";
316d1e34a8aSThierry Reding				nvidia,function = "i2c2";
317d1e34a8aSThierry Reding			};
318d1e34a8aSThierry Reding		};
319ecc295bbSStephen Warren	};
320ecc295bbSStephen Warren
3212a5fdc9aSStephen Warren	i2s@70002800 {
3222a5fdc9aSStephen Warren		status = "okay";
323c04abb3aSStephen Warren	};
324c04abb3aSStephen Warren
325c04abb3aSStephen Warren	serial@70006300 {
326*9766116aSThierry Reding		/delete-property/ dmas;
327*9766116aSThierry Reding		/delete-property/ dma-names;
3282a5fdc9aSStephen Warren		status = "okay";
329c04abb3aSStephen Warren	};
330c04abb3aSStephen Warren
3311771a254SStephen Warren	pwm: pwm@7000a000 {
3321771a254SStephen Warren		status = "okay";
3331771a254SStephen Warren	};
3341771a254SStephen Warren
33588950f3bSStephen Warren	i2c@7000c000 {
3362a5fdc9aSStephen Warren		status = "okay";
33788950f3bSStephen Warren		clock-frequency = <400000>;
338797acf70SStephen Warren
339797acf70SStephen Warren		wm8903: wm8903@1a {
340797acf70SStephen Warren			compatible = "wlf,wm8903";
341797acf70SStephen Warren			reg = <0x1a>;
342797acf70SStephen Warren			interrupt-parent = <&gpio>;
3436cecf916SStephen Warren			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
344797acf70SStephen Warren
345797acf70SStephen Warren			gpio-controller;
346797acf70SStephen Warren			#gpio-cells = <2>;
347797acf70SStephen Warren
348797acf70SStephen Warren			micdet-cfg = <0>;
349797acf70SStephen Warren			micdet-delay = <100>;
350797acf70SStephen Warren			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
351797acf70SStephen Warren		};
352b46b0b54SLaxman Dewangan
353b46b0b54SLaxman Dewangan		/* ALS and proximity sensor */
354b46b0b54SLaxman Dewangan		isl29018@44 {
355b46b0b54SLaxman Dewangan			compatible = "isil,isl29018";
356b46b0b54SLaxman Dewangan			reg = <0x44>;
357b46b0b54SLaxman Dewangan			interrupt-parent = <&gpio>;
3586cecf916SStephen Warren			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
359b46b0b54SLaxman Dewangan		};
36088950f3bSStephen Warren	};
36188950f3bSStephen Warren
36288950f3bSStephen Warren	i2c@7000c400 {
3632a5fdc9aSStephen Warren		status = "okay";
36497d5520fSStephen Warren		clock-frequency = <100000>;
36588950f3bSStephen Warren	};
36688950f3bSStephen Warren
36788950f3bSStephen Warren	i2c@7000c500 {
3682a5fdc9aSStephen Warren		status = "okay";
36988950f3bSStephen Warren		clock-frequency = <400000>;
37088950f3bSStephen Warren	};
37188950f3bSStephen Warren
37288950f3bSStephen Warren	i2c@7000d000 {
3732a5fdc9aSStephen Warren		status = "okay";
37488950f3bSStephen Warren		clock-frequency = <400000>;
375017a0104SStephen Warren
376017a0104SStephen Warren		pmic: tps6586x@34 {
377017a0104SStephen Warren			compatible = "ti,tps6586x";
378017a0104SStephen Warren			reg = <0x34>;
3796cecf916SStephen Warren			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
380017a0104SStephen Warren
38144b12ef7SStephen Warren			ti,system-power-controller;
38244b12ef7SStephen Warren
383017a0104SStephen Warren			#gpio-cells = <2>;
384017a0104SStephen Warren			gpio-controller;
385017a0104SStephen Warren
386017a0104SStephen Warren			sys-supply = <&vdd_5v0_reg>;
387017a0104SStephen Warren			vin-sm0-supply = <&sys_reg>;
388017a0104SStephen Warren			vin-sm1-supply = <&sys_reg>;
389017a0104SStephen Warren			vin-sm2-supply = <&sys_reg>;
390017a0104SStephen Warren			vinldo01-supply = <&sm2_reg>;
391017a0104SStephen Warren			vinldo23-supply = <&sm2_reg>;
392017a0104SStephen Warren			vinldo4-supply = <&sm2_reg>;
393017a0104SStephen Warren			vinldo678-supply = <&sm2_reg>;
394017a0104SStephen Warren			vinldo9-supply = <&sm2_reg>;
395017a0104SStephen Warren
396017a0104SStephen Warren			regulators {
397b9c665d7SStephen Warren				sys_reg: sys {
398017a0104SStephen Warren					regulator-name = "vdd_sys";
399017a0104SStephen Warren					regulator-always-on;
400017a0104SStephen Warren				};
401017a0104SStephen Warren
40282d3d459SDmitry Osipenko				vdd_core: sm0 {
403017a0104SStephen Warren					regulator-name = "vdd_sm0,vdd_core";
40482d3d459SDmitry Osipenko					regulator-min-microvolt = <950000>;
40582d3d459SDmitry Osipenko					regulator-max-microvolt = <1300000>;
40682d3d459SDmitry Osipenko					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
40782d3d459SDmitry Osipenko					regulator-coupled-max-spread = <170000 550000>;
408017a0104SStephen Warren					regulator-always-on;
40982d3d459SDmitry Osipenko					regulator-boot-on;
41082d3d459SDmitry Osipenko
41182d3d459SDmitry Osipenko					nvidia,tegra-core-regulator;
412017a0104SStephen Warren				};
413017a0104SStephen Warren
41482d3d459SDmitry Osipenko				vdd_cpu: sm1 {
415017a0104SStephen Warren					regulator-name = "vdd_sm1,vdd_cpu";
41682d3d459SDmitry Osipenko					regulator-min-microvolt = <750000>;
41782d3d459SDmitry Osipenko					regulator-max-microvolt = <1125000>;
41882d3d459SDmitry Osipenko					regulator-coupled-with = <&vdd_core &rtc_vdd>;
41982d3d459SDmitry Osipenko					regulator-coupled-max-spread = <550000 550000>;
420017a0104SStephen Warren					regulator-always-on;
42182d3d459SDmitry Osipenko					regulator-boot-on;
42282d3d459SDmitry Osipenko
42382d3d459SDmitry Osipenko					nvidia,tegra-cpu-regulator;
424017a0104SStephen Warren				};
425017a0104SStephen Warren
426b9c665d7SStephen Warren				sm2_reg: sm2 {
427017a0104SStephen Warren					regulator-name = "vdd_sm2,vin_ldo*";
428017a0104SStephen Warren					regulator-min-microvolt = <3700000>;
429017a0104SStephen Warren					regulator-max-microvolt = <3700000>;
430017a0104SStephen Warren					regulator-always-on;
431017a0104SStephen Warren				};
432017a0104SStephen Warren
433017a0104SStephen Warren				/* LDO0 is not connected to anything */
434017a0104SStephen Warren
435b9c665d7SStephen Warren				ldo1 {
436017a0104SStephen Warren					regulator-name = "vdd_ldo1,avdd_pll*";
437017a0104SStephen Warren					regulator-min-microvolt = <1100000>;
438017a0104SStephen Warren					regulator-max-microvolt = <1100000>;
439017a0104SStephen Warren					regulator-always-on;
440017a0104SStephen Warren				};
441017a0104SStephen Warren
44282d3d459SDmitry Osipenko				rtc_vdd: ldo2 {
443017a0104SStephen Warren					regulator-name = "vdd_ldo2,vdd_rtc";
44482d3d459SDmitry Osipenko					regulator-min-microvolt = <950000>;
44582d3d459SDmitry Osipenko					regulator-max-microvolt = <1300000>;
44682d3d459SDmitry Osipenko					regulator-coupled-with = <&vdd_core &vdd_cpu>;
44782d3d459SDmitry Osipenko					regulator-coupled-max-spread = <170000 550000>;
44882d3d459SDmitry Osipenko					regulator-always-on;
44982d3d459SDmitry Osipenko					regulator-boot-on;
45082d3d459SDmitry Osipenko
45182d3d459SDmitry Osipenko					nvidia,tegra-rtc-regulator;
452017a0104SStephen Warren				};
453017a0104SStephen Warren
454b9c665d7SStephen Warren				ldo3 {
455017a0104SStephen Warren					regulator-name = "vdd_ldo3,avdd_usb*";
456017a0104SStephen Warren					regulator-min-microvolt = <3300000>;
457017a0104SStephen Warren					regulator-max-microvolt = <3300000>;
458017a0104SStephen Warren					regulator-always-on;
459017a0104SStephen Warren				};
460017a0104SStephen Warren
461b9c665d7SStephen Warren				ldo4 {
462017a0104SStephen Warren					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
463017a0104SStephen Warren					regulator-min-microvolt = <1800000>;
464017a0104SStephen Warren					regulator-max-microvolt = <1800000>;
465017a0104SStephen Warren					regulator-always-on;
466017a0104SStephen Warren				};
467017a0104SStephen Warren
468b9c665d7SStephen Warren				ldo5 {
469017a0104SStephen Warren					regulator-name = "vdd_ldo5,vcore_mmc";
470017a0104SStephen Warren					regulator-min-microvolt = <2850000>;
471017a0104SStephen Warren					regulator-max-microvolt = <2850000>;
472017a0104SStephen Warren					regulator-always-on;
473017a0104SStephen Warren				};
474017a0104SStephen Warren
475b9c665d7SStephen Warren				ldo6 {
476017a0104SStephen Warren					regulator-name = "vdd_ldo6,avdd_vdac";
477017a0104SStephen Warren					regulator-min-microvolt = <1800000>;
478017a0104SStephen Warren					regulator-max-microvolt = <1800000>;
479017a0104SStephen Warren				};
480017a0104SStephen Warren
48197d5520fSStephen Warren				hdmi_vdd_reg: ldo7 {
482017a0104SStephen Warren					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
483017a0104SStephen Warren					regulator-min-microvolt = <3300000>;
484017a0104SStephen Warren					regulator-max-microvolt = <3300000>;
485017a0104SStephen Warren				};
486017a0104SStephen Warren
48797d5520fSStephen Warren				hdmi_pll_reg: ldo8 {
488017a0104SStephen Warren					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
489017a0104SStephen Warren					regulator-min-microvolt = <1800000>;
490017a0104SStephen Warren					regulator-max-microvolt = <1800000>;
491017a0104SStephen Warren				};
492017a0104SStephen Warren
493b9c665d7SStephen Warren				ldo9 {
494017a0104SStephen Warren					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
495017a0104SStephen Warren					regulator-min-microvolt = <2850000>;
496017a0104SStephen Warren					regulator-max-microvolt = <2850000>;
497017a0104SStephen Warren					regulator-always-on;
498017a0104SStephen Warren				};
499017a0104SStephen Warren
500b9c665d7SStephen Warren				ldo_rtc {
501017a0104SStephen Warren					regulator-name = "vdd_rtc_out,vdd_cell";
502017a0104SStephen Warren					regulator-min-microvolt = <3300000>;
503017a0104SStephen Warren					regulator-max-microvolt = <3300000>;
504017a0104SStephen Warren					regulator-always-on;
505017a0104SStephen Warren				};
506017a0104SStephen Warren			};
507017a0104SStephen Warren		};
508ee9f7260SThierry Reding
5093744c7d8SDmitry Osipenko		nct1008: temperature-sensor@4c {
510ee9f7260SThierry Reding			compatible = "onnn,nct1008";
511ee9f7260SThierry Reding			reg = <0x4c>;
5123744c7d8SDmitry Osipenko			#thermal-sensor-cells = <1>;
513ee9f7260SThierry Reding		};
514017a0104SStephen Warren	};
515017a0104SStephen Warren
51658ecb23fSStephen Warren	pmc@7000e400 {
517017a0104SStephen Warren		nvidia,invert-interrupt;
51847d2d63bSJoseph Lo		nvidia,suspend-mode = <1>;
519a44a019dSJoseph Lo		nvidia,cpu-pwr-good-time = <2000>;
520a44a019dSJoseph Lo		nvidia,cpu-pwr-off-time = <100>;
521a44a019dSJoseph Lo		nvidia,core-pwr-good-time = <3845 3845>;
522a44a019dSJoseph Lo		nvidia,core-pwr-off-time = <458>;
523a44a019dSJoseph Lo		nvidia,sys-clock-req-active-high;
52483b7f0b8SDmitry Osipenko		core-supply = <&vdd_core>;
52588950f3bSStephen Warren	};
52688950f3bSStephen Warren
5272a5fdc9aSStephen Warren	usb@c5000000 {
5282a5fdc9aSStephen Warren		status = "okay";
5292a5fdc9aSStephen Warren	};
5302a5fdc9aSStephen Warren
5314c94c8b5SVenu Byravarasu	usb-phy@c5000000 {
5324c94c8b5SVenu Byravarasu		status = "okay";
5334c94c8b5SVenu Byravarasu	};
5344c94c8b5SVenu Byravarasu
535c04abb3aSStephen Warren	usb@c5004000 {
5362a5fdc9aSStephen Warren		status = "okay";
5379dffe3beSVenu Byravarasu	};
5389dffe3beSVenu Byravarasu
5399dffe3beSVenu Byravarasu	usb-phy@c5004000 {
5404c94c8b5SVenu Byravarasu		status = "okay";
5413325f1bcSStephen Warren		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
5423325f1bcSStephen Warren			GPIO_ACTIVE_LOW>;
543c04abb3aSStephen Warren	};
544c04abb3aSStephen Warren
5452a5fdc9aSStephen Warren	usb@c5008000 {
5462a5fdc9aSStephen Warren		status = "okay";
547c04abb3aSStephen Warren	};
548c04abb3aSStephen Warren
5494c94c8b5SVenu Byravarasu	usb-phy@c5008000 {
5504c94c8b5SVenu Byravarasu		status = "okay";
5514c94c8b5SVenu Byravarasu	};
5524c94c8b5SVenu Byravarasu
55332c096c2SThierry Reding	mmc@c8000000 {
554c729429eSWei Ni		status = "okay";
5553325f1bcSStephen Warren		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
556c729429eSWei Ni		bus-width = <4>;
5577a2617a6SJoseph Lo		keep-power-in-suspend;
558c729429eSWei Ni	};
559c729429eSWei Ni
56032c096c2SThierry Reding	mmc@c8000400 {
5612a5fdc9aSStephen Warren		status = "okay";
5623325f1bcSStephen Warren		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
5633325f1bcSStephen Warren		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
5643325f1bcSStephen Warren		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
565deb88cc3SArnd Bergmann		bus-width = <4>;
566c04abb3aSStephen Warren	};
567c04abb3aSStephen Warren
56832c096c2SThierry Reding	mmc@c8000600 {
5692a5fdc9aSStephen Warren		status = "okay";
570deb88cc3SArnd Bergmann		bus-width = <8>;
5717a2617a6SJoseph Lo		non-removable;
572c04abb3aSStephen Warren	};
573c04abb3aSStephen Warren
5741771a254SStephen Warren	backlight: backlight {
5751771a254SStephen Warren		compatible = "pwm-backlight";
5761771a254SStephen Warren
5771771a254SStephen Warren		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
5781771a254SStephen Warren		power-supply = <&vdd_bl_reg>;
5791771a254SStephen Warren		pwms = <&pwm 2 5000000>;
5801771a254SStephen Warren
5811771a254SStephen Warren		brightness-levels = <0 4 8 16 32 64 128 255>;
5821771a254SStephen Warren		default-brightness-level = <6>;
5831771a254SStephen Warren	};
5841771a254SStephen Warren
5854f74ed81SDavid Heidelberg	clk32k_in: clock-32k {
5867021d122SJoseph Lo		compatible = "fixed-clock";
5877021d122SJoseph Lo		clock-frequency = <32768>;
588901c8653SThierry Reding		#clock-cells = <0>;
5897021d122SJoseph Lo	};
5907021d122SJoseph Lo
591bd7cd7e0SJon Hunter	cpus {
592bd7cd7e0SJon Hunter		cpu0: cpu@0 {
59382d3d459SDmitry Osipenko			cpu-supply = <&vdd_cpu>;
594bd7cd7e0SJon Hunter			operating-points-v2 = <&cpu0_opp_table>;
5953744c7d8SDmitry Osipenko			#cooling-cells = <2>;
596bd7cd7e0SJon Hunter		};
597bd7cd7e0SJon Hunter
5983744c7d8SDmitry Osipenko		cpu1: cpu@1 {
59982d3d459SDmitry Osipenko			cpu-supply = <&vdd_cpu>;
600bd7cd7e0SJon Hunter			operating-points-v2 = <&cpu0_opp_table>;
6013744c7d8SDmitry Osipenko			#cooling-cells = <2>;
602bd7cd7e0SJon Hunter		};
603bd7cd7e0SJon Hunter	};
604bd7cd7e0SJon Hunter
6055741a256SJoseph Lo	gpio-keys {
6065741a256SJoseph Lo		compatible = "gpio-keys";
6075741a256SJoseph Lo
608799270e9SKrzysztof Kozlowski		key-power {
6095741a256SJoseph Lo			label = "Power";
6103325f1bcSStephen Warren			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
6116bccbd5eSLaxman Dewangan			linux,code = <KEY_POWER>;
612d1c04d30SSudeep Holla			wakeup-source;
6135741a256SJoseph Lo		};
6145741a256SJoseph Lo	};
6155741a256SJoseph Lo
616d1e34a8aSThierry Reding	i2cmux {
617d1e34a8aSThierry Reding		compatible = "i2c-mux-pinctrl";
618d1e34a8aSThierry Reding		#address-cells = <1>;
619d1e34a8aSThierry Reding		#size-cells = <0>;
620d1e34a8aSThierry Reding
621d1e34a8aSThierry Reding		i2c-parent = <&{/i2c@7000c400}>;
622d1e34a8aSThierry Reding
623d1e34a8aSThierry Reding		pinctrl-names = "ddc", "pta", "idle";
624d1e34a8aSThierry Reding		pinctrl-0 = <&state_i2cmux_ddc>;
625d1e34a8aSThierry Reding		pinctrl-1 = <&state_i2cmux_pta>;
626d1e34a8aSThierry Reding		pinctrl-2 = <&state_i2cmux_idle>;
627d1e34a8aSThierry Reding
628d1e34a8aSThierry Reding		hdmi_ddc: i2c@0 {
629d1e34a8aSThierry Reding			reg = <0>;
630d1e34a8aSThierry Reding			#address-cells = <1>;
631d1e34a8aSThierry Reding			#size-cells = <0>;
632d1e34a8aSThierry Reding		};
633d1e34a8aSThierry Reding
634d1e34a8aSThierry Reding		lvds_ddc: i2c@1 {
635d1e34a8aSThierry Reding			reg = <1>;
636d1e34a8aSThierry Reding			#address-cells = <1>;
637d1e34a8aSThierry Reding			#size-cells = <0>;
638d1e34a8aSThierry Reding		};
639d1e34a8aSThierry Reding	};
640d1e34a8aSThierry Reding
6411771a254SStephen Warren	panel: panel {
6427860c873SRob Herring		compatible = "chunghwa,claa101wa01a";
6431771a254SStephen Warren
6441771a254SStephen Warren		power-supply = <&vdd_pnl_reg>;
6451771a254SStephen Warren		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
6461771a254SStephen Warren
6471771a254SStephen Warren		backlight = <&backlight>;
6481771a254SStephen Warren		ddc-i2c-bus = <&lvds_ddc>;
6491771a254SStephen Warren	};
6501771a254SStephen Warren
651c629196dSDmitry Osipenko	vdd_5v0_reg: regulator-5v0 {
652017a0104SStephen Warren		compatible = "regulator-fixed";
653017a0104SStephen Warren		regulator-name = "vdd_5v0";
654017a0104SStephen Warren		regulator-min-microvolt = <5000000>;
655017a0104SStephen Warren		regulator-max-microvolt = <5000000>;
656017a0104SStephen Warren		regulator-always-on;
657017a0104SStephen Warren	};
658017a0104SStephen Warren
659c629196dSDmitry Osipenko	regulator-1v5 {
660017a0104SStephen Warren		compatible = "regulator-fixed";
661017a0104SStephen Warren		regulator-name = "vdd_1v5";
662017a0104SStephen Warren		regulator-min-microvolt = <1500000>;
663017a0104SStephen Warren		regulator-max-microvolt = <1500000>;
6643325f1bcSStephen Warren		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
665017a0104SStephen Warren	};
666017a0104SStephen Warren
667c629196dSDmitry Osipenko	regulator-1v2 {
668017a0104SStephen Warren		compatible = "regulator-fixed";
669017a0104SStephen Warren		regulator-name = "vdd_1v2";
670017a0104SStephen Warren		regulator-min-microvolt = <1200000>;
671017a0104SStephen Warren		regulator-max-microvolt = <1200000>;
6723325f1bcSStephen Warren		gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
673017a0104SStephen Warren		enable-active-high;
674017a0104SStephen Warren	};
675017a0104SStephen Warren
676c629196dSDmitry Osipenko	vdd_pnl_reg: regulator-pnl {
677017a0104SStephen Warren		compatible = "regulator-fixed";
678017a0104SStephen Warren		regulator-name = "vdd_pnl";
679017a0104SStephen Warren		regulator-min-microvolt = <2800000>;
680017a0104SStephen Warren		regulator-max-microvolt = <2800000>;
6813325f1bcSStephen Warren		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
682017a0104SStephen Warren		enable-active-high;
683017a0104SStephen Warren	};
684017a0104SStephen Warren
685c629196dSDmitry Osipenko	vdd_bl_reg: regulator-bl {
686017a0104SStephen Warren		compatible = "regulator-fixed";
687017a0104SStephen Warren		regulator-name = "vdd_bl";
688017a0104SStephen Warren		regulator-min-microvolt = <2800000>;
689017a0104SStephen Warren		regulator-max-microvolt = <2800000>;
6903325f1bcSStephen Warren		gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
691017a0104SStephen Warren		enable-active-high;
692017a0104SStephen Warren	};
693017a0104SStephen Warren
694797acf70SStephen Warren	sound {
695797acf70SStephen Warren		compatible = "nvidia,tegra-audio-wm8903-ventana",
696797acf70SStephen Warren			     "nvidia,tegra-audio-wm8903";
697797acf70SStephen Warren		nvidia,model = "NVIDIA Tegra Ventana";
698797acf70SStephen Warren
699797acf70SStephen Warren		nvidia,audio-routing =
700797acf70SStephen Warren			"Headphone Jack", "HPOUTR",
701797acf70SStephen Warren			"Headphone Jack", "HPOUTL",
702797acf70SStephen Warren			"Int Spk", "ROP",
703797acf70SStephen Warren			"Int Spk", "RON",
704797acf70SStephen Warren			"Int Spk", "LOP",
705797acf70SStephen Warren			"Int Spk", "LON",
706797acf70SStephen Warren			"Mic Jack", "MICBIAS",
707797acf70SStephen Warren			"IN1L", "Mic Jack";
708797acf70SStephen Warren
709797acf70SStephen Warren		nvidia,i2s-controller = <&tegra_i2s1>;
710797acf70SStephen Warren		nvidia,audio-codec = <&wm8903>;
711797acf70SStephen Warren
7123325f1bcSStephen Warren		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
7135f45da70SDmitry Osipenko		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
7143325f1bcSStephen Warren		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
7153325f1bcSStephen Warren			GPIO_ACTIVE_HIGH>;
7163325f1bcSStephen Warren		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
7173325f1bcSStephen Warren			GPIO_ACTIVE_HIGH>;
718f9cd2b3bSStephen Warren
719885a8cfaSHiroshi Doyu		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
720885a8cfaSHiroshi Doyu			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
721885a8cfaSHiroshi Doyu			 <&tegra_car TEGRA20_CLK_CDEV1>;
722f9cd2b3bSStephen Warren		clock-names = "pll_a", "pll_a_out0", "mclk";
723797acf70SStephen Warren	};
7243744c7d8SDmitry Osipenko
7253744c7d8SDmitry Osipenko	thermal-zones {
7263744c7d8SDmitry Osipenko		cpu-thermal {
7273744c7d8SDmitry Osipenko			polling-delay-passive = <1000>; /* milliseconds */
7283744c7d8SDmitry Osipenko			polling-delay = <5000>; /* milliseconds */
7293744c7d8SDmitry Osipenko
7303744c7d8SDmitry Osipenko			thermal-sensors = <&nct1008 1>;
7313744c7d8SDmitry Osipenko
7323744c7d8SDmitry Osipenko			trips {
7333744c7d8SDmitry Osipenko				trip0: cpu-alert0 {
7343744c7d8SDmitry Osipenko					/* start throttling at 50C */
7353744c7d8SDmitry Osipenko					temperature = <50000>;
7363744c7d8SDmitry Osipenko					hysteresis = <200>;
7373744c7d8SDmitry Osipenko					type = "passive";
7383744c7d8SDmitry Osipenko				};
7393744c7d8SDmitry Osipenko
7403744c7d8SDmitry Osipenko				trip1: cpu-crit {
7413744c7d8SDmitry Osipenko					/* shut down at 60C */
7423744c7d8SDmitry Osipenko					temperature = <60000>;
7433744c7d8SDmitry Osipenko					hysteresis = <2000>;
7443744c7d8SDmitry Osipenko					type = "critical";
7453744c7d8SDmitry Osipenko				};
7463744c7d8SDmitry Osipenko			};
7473744c7d8SDmitry Osipenko
7483744c7d8SDmitry Osipenko			cooling-maps {
7493744c7d8SDmitry Osipenko				map0 {
7503744c7d8SDmitry Osipenko					trip = <&trip0>;
7513744c7d8SDmitry Osipenko					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7523744c7d8SDmitry Osipenko							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7533744c7d8SDmitry Osipenko				};
7543744c7d8SDmitry Osipenko			};
7553744c7d8SDmitry Osipenko		};
7563744c7d8SDmitry Osipenko	};
757add29e61SPeter De Schrijver};
758