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/linux/drivers/clocksource/
H A Dtimer-microchip-pit64b.c54 * @gclk: PIT64B's generic clock
60 struct clk *gclk; member
139 clk_disable_unprepare(timer->gclk); in mchp_pit64b_suspend()
147 clk_prepare_enable(timer->gclk); in mchp_pit64b_resume()
261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
266 * This function, first tries to use GCLK by requesting the desired rate from
268 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
278 * | |-->gclk -->|-->| | +---------+ +-----+ |
[all …]
/linux/sound/soc/atmel/
H A Dmchp-i2s-mcc.c251 struct clk *gclk; member
456 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
460 dev_err(dev->dev, "gclk error for rate %lu: %d", in mchp_i2s_mcc_config_divs()
464 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n", in mchp_i2s_mcc_config_divs()
492 best_clk == dev->pclk ? "pclk" : "gclk", in mchp_i2s_mcc_config_divs()
500 if (best_clk == dev->gclk) in mchp_i2s_mcc_config_divs()
730 ret = clk_set_rate(dev->gclk, rate); in mchp_i2s_mcc_hw_params()
733 "unable to set rate %lu to GCLK: %d\n", in mchp_i2s_mcc_hw_params()
738 ret = clk_prepare(dev->gclk); in mchp_i2s_mcc_hw_params()
740 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); in mchp_i2s_mcc_hw_params()
[all …]
H A Datmel-i2s.c200 struct clk *gclk; member
298 if (!dev->gclk) { in atmel_i2s_get_gck_param()
445 clk_disable_unprepare(dev->gclk); in atmel_i2s_switch_mck_generator()
455 ret = clk_set_rate(dev->gclk, gclk_rate); in atmel_i2s_switch_mck_generator()
459 ret = clk_prepare_enable(dev->gclk); in atmel_i2s_switch_mck_generator()
580 if (!dev->gclk) in atmel_i2s_sama5d2_mck_init()
594 return clk_set_parent(muxclk, dev->gclk); in atmel_i2s_sama5d2_mck_init()
665 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_i2s_probe()
666 if (IS_ERR(dev->gclk)) { in atmel_i2s_probe()
667 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) in atmel_i2s_probe()
[all …]
H A Datmel-pdmic.c31 struct clk *gclk; member
111 ret = clk_prepare_enable(dd->gclk); in atmel_pdmic_cpu_dai_startup()
117 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_startup()
141 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_shutdown()
406 gclk_rate = clk_get_rate(dd->gclk); in atmel_pdmic_cpu_dai_hw_params()
527 u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8); in atmel_pdmic_get_sample_rate()
602 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_pdmic_probe()
603 if (IS_ERR(dd->gclk)) { in atmel_pdmic_probe()
604 ret = PTR_ERR(dd->gclk); in atmel_pdmic_probe()
609 /* The gclk clock frequency must always be three times in atmel_pdmic_probe()
[all …]
H A Dmchp-pdmc.c120 struct clk *gclk; member
569 round_rate = clk_round_rate(dd->gclk, in mchp_pdmc_hw_params()
586 clk_disable_unprepare(dd->gclk); in mchp_pdmc_hw_params()
589 ret = clk_set_rate(dd->gclk, gclk_rate); in mchp_pdmc_hw_params()
590 clk_prepare_enable(dd->gclk); in mchp_pdmc_hw_params()
592 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", in mchp_pdmc_hw_params()
974 clk_disable_unprepare(dd->gclk); in mchp_pdmc_runtime_suspend()
991 ret = clk_prepare_enable(dd->gclk); in mchp_pdmc_runtime_resume()
1003 clk_disable_unprepare(dd->gclk); in mchp_pdmc_runtime_resume()
1041 dd->gclk = devm_clk_get(dev, "gclk"); in mchp_pdmc_probe()
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi78 compatible = "renesas,emev2-smu-gclk";
90 compatible = "renesas,emev2-smu-gclk";
127 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,emev2-smu-gclk";
139 compatible = "renesas,emev2-smu-gclk";
145 compatible = "renesas,emev2-smu-gclk";
151 compatible = "renesas,emev2-smu-gclk";
/linux/drivers/pwm/
H A Dpwm-atmel-tcb.c55 struct clk *gclk; member
276 * If there is a gclk, the first divisor is actually the gclk selector in atmel_tcb_pwm_config()
278 if (tcbpwmc->gclk) in atmel_tcb_pwm_config()
426 tcbpwmc->gclk = of_clk_get_by_name(np->parent, "gclk"); in atmel_tcb_pwm_probe()
427 if (IS_ERR(tcbpwmc->gclk)) { in atmel_tcb_pwm_probe()
428 err = PTR_ERR(tcbpwmc->gclk); in atmel_tcb_pwm_probe()
455 clk_put(tcbpwmc->gclk); in atmel_tcb_pwm_probe()
474 clk_put(tcbpwmc->gclk); in atmel_tcb_pwm_remove()
/linux/Documentation/devicetree/bindings/sound/
H A Datmel,sama5d2-i2s.yaml34 with gclk when Master Mode is required.
40 - const: gclk
82 clock-names = "pclk", "gclk", "muxclk";
H A Dmicrochip,sama7g5-spdiftx.yaml40 - const: gclk
75 clock-names = "pclk", "gclk";
H A Dmicrochip,sama7g5-spdifrx.yaml40 - const: gclk
75 clock-names = "pclk", "gclk";
H A Datmel,sama5d2-pdmic.yaml36 - const: gclk
91 clock-names = "pclk", "gclk";
H A Datmel,sama5d2-classd.yaml46 - const: gclk
98 clock-names = "pclk", "gclk";
H A Dmicrochip,sama7g5-pdmc.yaml40 - const: gclk
100 clock-names = "pclk", "gclk";
H A Dmicrochip,sama7g5-i2smcc.yaml52 - const: gclk
112 clock-names = "pclk", "gclk";
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,emev2-smu.yaml81 const: renesas,emev2-smu-gclk
135 compatible = "renesas,emev2-smu-gclk";
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c149 int gclk = cstate->domain[nv_clk_src_core]; in nv40_clk_calc() local
155 ret = nv40_clk_calc_pll(clk, 0x004000, gclk, in nv40_clk_calc()
169 if (sclk && sclk != gclk) { in nv40_clk_calc()
/linux/drivers/spi/
H A Datmel-quadspi.c274 struct clk *gclk; member
1051 /* Disable DLL before setting GCLK */ in atmel_qspi_set_gclk()
1068 ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); in atmel_qspi_set_gclk()
1075 ret = clk_prepare_enable(aq->gclk); in atmel_qspi_set_gclk()
1398 aq->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_qspi_probe()
1399 if (IS_ERR(aq->gclk)) { in atmel_qspi_probe()
1401 err = PTR_ERR(aq->gclk); in atmel_qspi_probe()
1459 clk_disable_unprepare(aq->gclk); in atmel_qspi_sama7g5_suspend()
/linux/drivers/tty/serial/
H A Datmel_serial.c115 struct clk *gclk; /* uart generic clock */ member
2092 if (__clk_is_enabled(atmel_port->gclk)) in atmel_serial_pm()
2093 clk_disable_unprepare(atmel_port->gclk); in atmel_serial_pm()
2287 * if we use the GCLK as the clock source driving the baudrate in atmel_set_termios()
2291 if (__clk_is_enabled(atmel_port->gclk)) in atmel_set_termios()
2292 clk_disable_unprepare(atmel_port->gclk); in atmel_set_termios()
2293 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2297 clk_set_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2298 ret = clk_prepare_enable(atmel_port->gclk); in atmel_set_termios()
2310 * Set the Clock Divisor for GCLK to 1. in atmel_set_termios()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi424 pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
510 l3_gclk: clock-l3-gclk {
528 l4hs_gclk: clock-l4hs-gclk {
537 l3s_gclk: clock-l3s-gclk {
546 l4ls_gclk: clock-l4ls-gclk {
555 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
/linux/Documentation/devicetree/bindings/spi/
H A Datmel,quadspi.yaml43 - enum: [ qspick, gclk ]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d2.dtsi403 clock-names = "t0_clk", "gclk", "slow_clk";
413 clock-names = "t0_clk", "gclk", "slow_clk";
441 clock-names = "pclk", "gclk";
736 clock-names = "pclk", "gclk";
1120 clock-names = "pclk", "gclk";
1136 clock-names = "pclk", "gclk";
H A Dsam9x7.dtsi279 clock-names = "pclk", "gclk";
399 clock-names = "pclk", "gclk";
457 clock-names = "pclk", "gclk";
470 clock-names = "pclk", "gclk";
512 clock-names = "t0_clk", "gclk", "slow_clk";
/linux/drivers/clk/at91/
H A Dclk-generated.c62 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", in clk_generated_enable()
207 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", in clk_generated_determine_rate()
/linux/Documentation/devicetree/bindings/soc/microchip/
H A Datmel,at91rm9200-tcb.yaml123 - const: gclk
/linux/Documentation/devicetree/bindings/serial/
H A Datmel,at91-usart.yaml52 - const: gclk

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